Cirrus Logic EP7311 - Manual (Page 35)

DS506F2
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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 35
EP7311
High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
Table U. JTAG Boundary Scan Signal Ordering
PBGA
Ball
Signal Type Position
B1 nCS[5] O 1
C2 EXPCLK I/O 3
E4 WORD O 6
D1 WRITE/nSDRAS O 8
F5 RUN/CLKEN O 10
D2 EXPRDY I 13
F4 TXD2 O 14
E1 RXD2 I 16
E2 PB[7] I/O 17
G5 PB[6] I/O 20
F1 PB[5] I/O 23
G4 PB[4] I/O 26
F2 PB[3] I/O 29
H7 PB[2] I/O 32
G1 PB[1]/PRDY2 I/O 35
H6 PB[0]/PRDY1 I/O 38
H1 PA[7] I/O 41
H5 PA[6] I/O 44
H2 PA[5] I/O 47
H4 PA[4] I/O 50
J1 PA[3] I/O 53
J4 PA[2] I/O 56
J2 PA[1] I/O 59
J5 PA[0] I/O 62
K1 LEDDRV O 65
J6 TXD1 O 67
K2 PHDIN I 69
J7 CTS I 70
L1 RXD1 I 71
K4 DCD I 72
L2 DSR I 73
K5 nTEST1 I 74
M1 nTEST0 I 75
K6 EINT3 I 76
M2 nEINT2 I 77
L4 nEINT1 I 78