Cirrus Logic AN253 - Manual (Page 2)

AN253
2
- Conversion between floating point and integer data representations
- Sixteen (16) 64-bit general-purpose registers
- Four (4) 72-bit accumulators
- Status and control registers
2.2 Instruction Set
The MaverickCrunch coprocessor's instruction set is robust and includes memory, control, and arithmetic
operations. MaverickCrunch mnemonics are translated by the compiler or assembler into ARM coproces-
sor instructions. For example, the MaverickCrunch mnemonic for double precision floating-point multiply
is:
cfmuld c0, c1, c2
The equivalent ARM coprocessor instruction is:
cdp p4, 1, c0, c1, c2, 1
There are five categories of ARM coprocessor instructions: Data Path (CDP), Load (LDC), Store (STC),
Coprocessor to ARM Moves (MCR), and ARM to coprocessor moves (MRC). CDP instructions include all
arithmetic operations, and any other operation internal to the coprocessor. LDC and STC instructions in-
clude the set of operations responsible for moving data between memory and the coprocessor. MCR and
MRC instructions are responsible for moving data between ARM and coprocessor registers.
Table 1, Table 2 and Table 3 summarize all of the MaverickCrunch's instruction mnemonics. For more
information on the MaverickCrunch instruction set, please see the table:
MaverickCrunch Instruction Set
in the User's Guide.
Table 1. MaverickCrunch Load/Store Mnemonics
cfldrs Cd, [Rn] cfldrd Cd, [Rn] cfldr32 Cd, [Rn]
cfldr64 Cd, [Rn] cfstrs Cd, [Rn] cfstrd Cd, [Rn]
cflstr32 Cd, [Rn] cfstr64 Cd, [Rn] cfmvsr Cn, Rd
cfmvdlr Cn, Rd cfmvdhr Cn, Rd cfmv64lr Cn, Rd
cfmv64hr Cn, Rd cfmvsr Rd, Cn cfmvrdl Rd, Cn
cfmvrdh Rd, Cn cfmvr64l Rd, Cn cfmvr64h Rd, Cn
cfmval32 Cd, Cn cfmvam32 Cd, Cn cfmv32a Cd, Cn
cfmv64a Cd, Cn cfmvsc32 Cd, Cn cfmv32sc Cd, Cn
cfcpys Cd, Cn cfcpyd Cd, Cn