MSI RS482M2-IL/L - Manual (Page 47)

3-12
MS-7093 M-ATX Mainboard
M emclock Index Value (M hz)
User can place an artificial memory clock limit on the system. Please note that
memory is prevented from running faster than this frequency.
CAS# Latency (Tcl)
This controls the CAS latency, which determines the timing delay (in clock
cycles) before SDRAM starts a read command after receiving it. Settings:
[Auto], [2.0], [2.5], [3.0]. [2.0] increases the system performance the most while
[3.0] provides the most stable performance.
LDT & PCI Bus Control
Press <Enter> to enter the submenu and the following screen appears.
LDT Configuration
This item disables/enables the LDT configuration.
Upstream/Downstream LDT Bus Width
These two items control the utilized widths of the HyperTransport link. Setting
options: [8 bit], [16 bit].
LDT Bus Frequency
This item specifies the maximum operating frequency of the link's transmitter
clock.
PCIE Reset Delay
This item disables/enables the reset delay of the PCI Express slot.
Internal Video M ode
This setting specifies the internal video mode. Setting options: [Disabled], [UMA],
[UMA+SidePort], [SidePort].