B&B Electronics PCMCIA 232PCC2 - Manual (Page 12)

Documentation Number 232PCC23799 Manual 11
B&B Electronics Mfg Co Inc – 707 Dayton Rd - PO Box 1040 - Ottawa IL 61350 - Ph 815-433-5100 - Fax 815-433-5104
B&B Electronics Ltd – Westlink Commercial Park – Oranmore, Galway, Ireland – Ph +353-91-792444 – Fax +353-91-792445
Command Line Options
To configure a 232PCC2 in the system, the Enabler requires
one command line argument from the user to determine the
configuration of the card. This argument must be enclosed in
parenthesis and within the argument, any or all of the following
parameters may be specified using a comma (no spaces) to
separate each parameter:
Ssocket
specifies which PCMCIA socket the 232PCC2 must be
inserted into for this configuration argument to be used.
socket must be in the range 0 - 15. This option is
always required.
Baddress specifies a block mode base I/O adddress of the
232PCC2 in hexadecimal and must reside on an even
16-byte (10H) boundary. Specify only one of the
following three options: Baddress, Dmode, or ‘R’. Use
of one of these options is always required.
Dmode
specifies a COM mode base I/O address configuration
for the 232PCC2. The ‘D1’ option configures the
232PCC2 at COM1/COM3 (3F8/3E8), and the ‘D2’
option configures the 232PCC2 at COM2/COM4
(2F8/2E8). Specify only one of the following three
options: Baddress, Dmode, ‘R’. Use of one of these
options is always required.
Iirq specifies the interrupt level (IRQ) of the 232PCC2 in
decimal. irq must be one of the following values: 3, 4,
5, 7, 9, 10, 11, 12, 14, 15, or 0 if no IRQ is desired.
This option is required if the 'R' option is not used.
Waddress specifies the base address of the memory window
required to configure the 232PCC2. Set address = D0
for a memory window at segment D000, address = D8
for a memory window at segment D800, etc. Valid
settings for address are C8, CC, D0, D4, D8, and DC.
If this option is omitted, a memory window at segment
D000 will be used.
U instructs the Enabler to disable the 232PCC2's
interrupt status register and enable the Scratchpad
registers of the individual UARTs. This option is only
required in very rare cases where an application
program requires access to the UART's Scratchpad
register. If this option is omitted, the 232PCC2's
interrupt status register is enabled and the UARTs'