Truth table, Burst address table (cy7c1318cv18, cy7c1320cv18), Write cycle descriptions – Cypress CY7C1316CV18 User Manual
Page 10: Burst address table
CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18
Document Number: 001-07160 Rev. *E
Page 10 of 29
Truth Table
The truth table for the CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 follows.
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H
L
L
D(A1) at K(t + 1)
↑ D(A2) at K(t + 1) ↑
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
L-H
L
H
Q(A1) at C(t + 1)
↑ Q(A2) at C(t + 2) ↑
NOP: No Operation
L-H
H
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Burst Address Table
(CY7C1318CV18, CY7C1320CV18)
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
Write Cycle Descriptions
The write cycle description table for CY7C1316CV18 and CY7C1318CV18 follows.
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
L
L
L–H
–
During the data portion of a write sequence
:
CY7C1316CV18
− both nibbles (D
[7:0]
) are written into the device,
CY7C1318CV18
− both bytes (D
[17:0]
) are written into the device.
L
L
–
L-H During the data portion of a write sequence
:
CY7C1316CV18
− both nibbles (D
[7:0]
) are written into the device,
CY7C1318CV18
− both bytes (D
[17:0]
) are written into the device.
L
H
L–H
–
During the data portion of a write sequence
:
CY7C1316CV18
− only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1318CV18
− only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
L
H
–
L–H During the data portion of a write sequence
:
CY7C1316CV18
− only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1318CV18
− only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
H
L
L–H
–
During the data portion of a write sequence
:
CY7C1316CV18
− only the upper nibble (D
[7:4]
) is written into the device, D
[3:0]
remains unaltered.
CY7C1318CV18
− only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
H
L
–
L–H During the data portion of a write sequence
:
CY7C1316CV18
− only the upper nibble (D
[7:4]
) is written into the device, D
[3:0]
remains unaltered.
CY7C1318CV18
− only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
H
H
L–H
–
No data is written into the devices during this portion of a write operation.
H
H
–
L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. On CY7C1318CV18 and CY7C1320CV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
sequence in the burst. On CY7C1316CV18 and CY7C1916CV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the
table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
,
and BWS
3
can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.