Cypress CY14B104L - Manual (Page 11)

CY14B104L, CY14B104N
Document #: 001-07102 Rev. *L Page 11 of 25
Figure 9. SRAM Write Cycle #2: CE Controlled [3, 17, 18, 19]
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled
[3, 17, 18, 19]
Data Output
Data Input Input Data Valid
High Impedance
Address Valid Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
'DWD2XWSXW
'DWD,QSXW ,QSXW'DWD9DOLG
+LJK,PSHGDQFH
$GGUHVV9DOLG $GGUHVV
W
:&
W
6'
W
+'
%+(%/(
:(
&(
W
6&(
W
6$
W
%:
W
+$
W
$:
W
3:(
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