Kontron COMe Starterkit Eval T2 - Manual (Page 178)

Carrier Board PCB Layout Guidelines
6.5. Routing Rules for High-Speed Differential Interfaces
The following is a list of suggestions for designing with high-speed differential signals. This
should help implement these interfaces while providing maximum COM Express
Carrier Board
performance.
●
Use controlled impedance PCB traces that match the specified differential impedance.
●
Keep the trace lengths of the differential signal pairs as short as possible.
● The differential signal pair traces should be trace-length matched and the maximum trace-
length mismatch should not exceed the specified values. Match each differential pair per
segment.
● Maintain parallelism and symmetry between differential signals with the trace spacing needed
to achieve the specified differential impedance.
●
Maintain phase- and length-matching throughout the whole routing trace.
●
Maintain maximum possible separation between the differential pairs and any high-speed
clocks/periodic signals (CMOS/TTL) and any connector leaving the PCB (such as, I/O
connectors, control and signal headers, or power connectors).
●
Route differential signals on the signal layer nearest to the ground plane using a minimum of
vias and corners. This will reduce signal reflections and impedance changes. Use GND
stitching vias when changing layers.
● It is best to put CMOS/TTL and differential signals on a different layer(s), which should be
isolated by the power and ground planes.
● Avoid tight bends. When it becomes necessary to turn 90°, use two 45° turns or an arc
instead of making a single 90° turn.
●
Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or
ICs that use, and/or generate, clocks.
●
Stubs on differential signals should be avoided due to the fact that stubs will cause signal
reflections and affect signal quality.
●
Keep the length of high-speed clock and periodic signal traces that run parallel to high-speed
signal lines at a minimum to avoid crosstalk. Based on EMI testing experience, the minimum
suggested spacing to clock signals is 50mil.
● Use a minimum of 20mil spacing between the differential signal pairs and other signal traces
for optimal signal quality. This helps to prevent crosstalk.
● Traces should be routed over a continuous GND plane. If this is not possible, a well
bypassed VCC plane can be used. Route all traces over continuous planes (GND or VCC)
with no interruptions. Avoid crossing over anti-etch if at all possible. Crossing over anti-etch
(split planes) increases inductance and radiation levels by forcing a greater loop area.
PICMG ® COM Express ® Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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