Kontron COMe Starterkit Eval T2 - Manual (Page 190)

Carrier Board PCB Layout Guidelines
6.6. Routing Rules for Single Ended Interfaces
The following is a list of suggestions for designing with single ended signals. This should help
implement these interfaces while providing maximum COM Express Carrier Board performance.
● Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or ICs that
use or generate clocks.
●
Avoid tight bends. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of
making a single 90° turn.
●
Stubs on signals should be avoided due to the fact that stubs will cause signal reflections and affect
signal quality.
●
Keep the length of high-speed clock and periodic signal traces that run parallel to high-speed signal
lines at a minimum to avoid crosstalk. Based on EMI testing experience, the minimum suggested
spacing to clock signals is 50mil.
● Route all traces over continuous planes with no interruptions (ground reference preferred). Avoid
crossing over anti-etch if at all possible. Crossing over anti-etch (split planes) increases inductance
and radiation levels by forcing a greater loop area.
● Route digital power and signal traces over the digital ground plane.
●
Position the bypassing and decoupling capacitors close to the IC pins with wide traces to reduce
impedance.
PICMG ® COM Express ® Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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