Kontron SMARC-sA3874i - Manual (Page 31)

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User’s Guide
3.2.15 Gigabit Ethernet Controller (GbE) Interface
The ULP-COM sA3874i module supports one GbE interface. This is accomplished by using TI Cortex A8 SoC’s
internal MAC in conjunction with Atheros PHY (AR8031). This is diagrammed below.
Figure 6: GbE Controller Implementation
E
D
G
E
F
IN
G
E
R
(J
3) SITARA CPU
(U7)
GBE PHY
ATHEROS
AR8031
(U22)
GBE_MDI0+
GBE_MDI0-
GBE_LINK100#
GBE_LINK_ACT#
11
12
26
23
P30
P29
P21
P25
RGMII0_TXD[0]
RGMII0_TXD[1]
P23
R23
36
37
31
30
28
27
GBE_MDI3+
GBE_MDI3-
20
21
P20
P19
GBE_MDI1+
GBE_MDI1-
14
15
P27
P26
GBE_MDI2+
GBE_MDI2-
17
18
P24
P23
GBE_LINK1000#
24 P22
RGMII0_TXD[2]
RGMII0_TXD[3]
R25
T23
38
39
RGMII0_RXD[0]
RGMII0_RXD[1]
RGMII0_RXD[2]
RGMII0_RXD[3]
G28
G27
F28
H26
RGMII0_TXCTL
RGMII0_TXC
34
35
J26
H27
32
33
L23
L24
RGMII0_RXCTL
RGMII0_RXC
MDCLK
MDIO
1
48
H28
P24
INT_ETH
5 J27