Switching characteristics – Cypress CY7C145 User Manual
Page 7
CY7C145, CY7C144
Document #: 38-06034 Rev. *D
Page 7 of 21
t
SD
Data Set-Up to Write End
10
15
15
25
ns
t
HD
Data Hold From Write End
0
0
0
0
ns
t
HZWE
R/W LOW to High Z
10
15
20
25
ns
t
LZWE
R/W HIGH to Low Z
3
3
3
3
ns
t
WDD
Write Pulse to Data Delay
30
50
60
70
ns
t
DDD
Write Data Valid to Read Data
Valid
25
30
35
40
ns
BUSY TIMING
t
BLA
BUSY LOW from Address
Match
15
20
20
30
ns
t
BHA
BUSY HIGH from Address
Mismatch
15
20
20
30
ns
t
BLC
BUSY LOW from CE LOW
15
20
20
30
ns
t
BHC
BUSY HIGH from CE HIGH
15
20
20
30
ns
t
PS
Port Set-Up for Priority
5
5
5
5
ns
t
WB
R/W LOW after BUSY LOW
0
0
0
0
ns
t
WH
R/W HIGH after BUSY HIGH
13
20
30
30
ns
t
BDD
BUSY HIGH to Data Valid
15
25
35
55
ns
INTERRUPT TIMING
t
INS
INT Set Time
15
25
25
35
ns
t
INR
INT Reset Time
15
25
25
35
ns
SEMAPHORE TIMING
t
SOP
SEM Flag Update Pulse (OE
or SEM)
10
10
15
20
ns
t
SWRD
SEM Flag Write to Read Time
5
5
5
5
ns
t
SPS
SEM Flag Contention
Window
5
5
5
5
ns
Notes
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
Switching Characteristics
Over the Operating Range
[9]
(continued)
Parameter
Description
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Min
Max
Min
Max
Min
Max
Min
Max