Switching waveforms, Switching characteristics – Cypress CY7C138 User Manual

Page 6

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CY7C138, CY7C139

Document #: 38-06037 Rev. *D

Page 6 of 17

t

HD

Data Hold From Write End

0

0

0

0

ns

t

HZWE

[11,12]

R/W LOW to High Z

10

15

20

25

ns

t

LZWE

[11,12]

R/W HIGH to Low Z

3

3

3

3

ns

t

WDD

[13]

Write Pulse to Data Delay

30

50

60

70

ns

t

DDD

[13]

Write Data Valid to Read Data Valid

25

30

35

40

ns

BUSY TIMING

[14]

t

BLA

BUSY LOW from Address Match

15

20

20

45

ns

t

BHA

BUSY HIGH from Address Mismatch

15

20

20

40

ns

t

BLC

BUSY LOW from CE LOW

15

20

20

40

ns

t

BHC

BUSY HIGH from CE HIGH

15

20

20

35

ns

t

PS

Port Set-Up for Priority

5

5

5

5

ns

t

WB

R/W LOW after BUSY LOW

0

0

0

0

ns

t

WH

R/W HIGH after BUSY HIGH

13

20

30

40

ns

t

BDD

[15]

BUSY HIGH to Data Valid

Note 15

Note 15

Note 15

Note 15

ns

INTERRUPT TIMING

[14]

t

INS

INT Set Time

15

25

25

30

ns

t

INR

INT Reset Time

15

25

25

30

ns

SEMAPHORE TIMING

t

SOP

SEM Flag Update Pulse (OE or SEM)

10

10

15

20

ns

t

SWRD

SEM Flag Write to Read Time

5

5

5

5

ns

t

SPS

SEM Flag Contention Window

5

5

5

5

ns

Switching Characteristics

Over the Operating Range

[9]

(continued)

Parameter

Description

7C138-15

7C139-15

7C138-25

7C139-25

7C138-35

7C139-35

7C138-55

7C139-55

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Notes

9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

I

OI

/I

OH

and 30-pF load capacitance.

10. At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

.

11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
15. t

BDD

is a calculated parameter and is the greater of t

WDD

– t

PWE

(actual) or t

DDD

– t

SD

(actual).

Switching Waveforms

Figure 3. Read Cycle No. 1 (Either Port Address Access)

[16, 17]

Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)

[16, 18, 19]

t

RC

t

AA

t

OHA

DATA VALID

PREVIOUS DATA VALID

DATA OUT

ADDRESS

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