Digilent 410-282P-KIT - Manual (Page 2)

Cmod S6™ Reference Manual
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Page 2 of 4
On power-up, if the FPGA detects a valid bitstream stored in the Quad SPI flash memory, the FPGA will
automatically configure itself with that bitstream. If necessary, the user can reconfigure the FPGA with a different
bitstream at any point after power-up using iMPACT or Adept.
2 FPGA
The Cmod S6 features a Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Of the 92 available unshared FPGA I/O pins, 46
are routed to through-hole pins on the DIP module, 24 are not connected, 14 are used by the programming
interface, and 7 drive on-board I/Os (4 leds, 2 pushbuttons, and 2 clock inputs). Several of the 46 signals connected
to FPGA pins are routed to clock buffers, and several are routed to matched pairs. Please see the schematic for
more information.
The Spartan 6 LX4 FPGA includes 3,840 6-LUT logic cells, 4,800 flip-flops, 216Kb of block RAM, 8 DSP slices, and two
clock management tiles, each with two DCMs and one PLL. The fabric can support internal clock speeds above
400MHz, allowing the Cmod S6 to host high-speed or complex designs. Please see the Spartan 6 user manual
available at
www.xilinx.com for more detailed information.
3 Power
The Cmod S6 can be powered either from a USB-connected computer, or from a power source connected to DIP
pin 24 that delivers voltage in the range of 5VDC to 15VDC (the power input on pin 24 is most useful when the
board is used in an embedded system or in a solderless breadboard). The two sources are diode-OR’ed on the
board, so both may be connected simultaneously.
The FPGA and other on-board devices require 3.3VDC and 1.2VDC – both of these voltages are generated from the
input supply using Texas Instrument’s TPS62170 switching regulators. Total current draw depends on FPGA
configuration. When about half the FPGA is configured and running at 8MHz, the board consumes about 180mA
from the main supply.
4 Clocks
An 8MHz and a 1Hz clock are available to the FPGA. Both are generated from the on board USB processor, both are
routed to clock inputs on the FPGA, and both run continuously. The 8MHz clock, called “FPGA-GCLK”, can be used
with the FPGA’s clock manager to create a wide range of frequencies, even beyond 200MHz. The 1Hz clock
provides a simple timing signal for basic experiments and low-frequency needs.
5 Quad SPI Flash Memory
The Cmod S6 includes a non-volatile 16Mbyte Spansion Quad SPI Flash that can store FPGA configuration files as
well as user data. The Spansion device supports the standard 4-wire SPI protocol, as well as the newer Quad I/O
and Dual I/O protocols at speeds from 50 MHz to 133 MHz, depending on the protocol and command used. For
more information on the SPI Flash memory, please see the “S25FL128S and S25FL256S Data Sheet” at
www.spansion.com .
To achieve the fastest programming speed over the Digilent USB-JTAG connection, when generating the bitstream
in Project Navigator, change the SPI bus width to four and enable bitsream compression. To do this, simply select
“Generate Programming File” and navigate to Process>Process Properties. In the pop-up menu, enable –g
Compress under “Synthesis Options” and set –g SPI_buswidth to four under “Configuration Options”.