Digilent 410-279P-KIT - Manual (Page 20)

ZYBO™ FPGA Board Reference Manual
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Page 20 of 26
A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data
based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal
defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn.
The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical
refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh
frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock
and 60 +/-1Hz refresh, the signal timings shown in Fig. 11 can be derived. Timings for sync pulse width and front
and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot
be displayed) are based on observations taken from actual VGA displays.
T
S
T
disp
T
pw
T
fp
T
bp
T
S
T
disp
T
pw
T
fp
T
bp
Sync pulse
Display time
Pulse width
Front porch
Back porch
16.7ms
15.36ms
64 us
320 us
928 us
416,800
384,000
1,600
8,000
23,200
521
480
2
10
29
Symbol Parameter
Time Clocks Lines
Vertical Sync
32 us
25.6 us
3.84 us
640 ns
1.92 us
800
640
96
16
48
Clks
Horiz. Sync
Time
Figure 11. Signal timings for a 640-pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh.
A VGA controller circuit, such as the one diagramed in Fig. 12, decodes the output of a horizontal-sync counter
driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a
given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to
generate VS signal timings, and you can use this counter to locate any given row. These two continually running
counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse
and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
Horizontal
Counter
Zero
Detect
3.84us
Detect
Horizontal
Synch
Set
Reset
Vertical
Counter
Zero
Detect
64us
Detect
Vertical
Synch
Set
Reset
CE
VS
HS
Pixel
CLK
Figure 12. VGA display controller block diagram.