Digilent 6015-410-001P-KIT - Manual (Page 9)

NetFPGA-1G-CML™ Board Reference Manual
Data is transferred to and from the PHYs via a Reduced Gigabit Media Independent Interface (RGMII). This is
similar to the Gigabit Media Independent Interface (GMII), which uses eight bits for both transmit and receive
data. RGMII achieves the same data rate with half the number of data bits and double-data-rate clocking. 1 Gbps
data transfers are thereby achieved using a 125MHz clock with four bits transferred on each clock edge for both
send and receive. This provides a significant reduction in the number of FPGA I/O pins required to support the four
Ethernet interfaces.
Xilinx provides Ethernet MAC IP that will support 10/100/1000 Mb/s via the ISE Design Suite Coregen tool and the
Vivado design suite. Please refer to Xilinx Product Guide PG051 LogiCORE IP Tri-Mode Ethernet MAC for more
information.
LED Action Meaning
RJ45 Top
Slow blink Connection Negotiation Complete
On Link activity present
RJ45 Bottom
Off No link activity
Fast blink Link activity present
Table 2. RJ-45 Ethernet Connector LED Function.
11 PIC Subsystem
NetFPGA-1G includes a 32-bit PIC microcontroller for managing USB OTG, real-time clock, and secure storage
interfacing. The PIC is pre-programmed with manufacturing test code and an ability to load FPGA bitstreams from
a USB memory stick. It is possible to re-program the PIC to support end-user applications that make use of various
other PIC subsystem features. This may be done via J14 using a PICKit 3 In-Circuit Debugger (Digilent p/n
PG164130).
To run the pre-programmed manufacturing test, first set up the NetFPGA-1G and host PC as described in Appendix
A: Manufacturing Test. When the board is powered on, the factory-loaded PIC firmware will search for the
bitstream “mfg_test.bit” on the USB flash drive and use it to configure the FPGA in slave serial mode. After the
FPGA has been configured, a test menu will be displayed on the terminal emulator window connected to the
PmodUSBUART, and the user can run the tests by following the menu prompts. If the board is set up as described
in Appendix A, all tests should pass.
The address map of the PIC I 2 C peripherals is shown in Table 3. The PIC is also connected to an MX25L12835E SPI
Serial Flash using general-purpose I/O ports for increased data storage. The flash's pins are connected to the PIC
ports as shown in Table 4.
To program the PIC device, connect a PICkit 3 to the NetFPGA-1G by placing a 1x6 pin header in the zig-zag
connector J14 and connect it to the PICkit 3 using a 6-pin cable. If Digilent's 6-pin Pmod cable is used, the white
indicator dot on the NetFPGA-1G side should be above pin 6, and the dot on the PICkit 3 side will be face-up and
opposite the white arrow on the PICkit 3. The PIC can then be programmed from Microchip's MPLAB X or MPLAB
IPE by selecting the PICkit 3 as the programming tool.
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