Digilent XUPV2P - Manual (Page 12)

May 2005 XUPV2P BSB support 12
Design Implementation
• A bunch of things happen under the hood!!
– An HDL representation of the design will be created in the hdl directory
– Each submodule is synthesized into netlists stored in subdirectories under
implementation
– Ngdbuild combines the netlists and performs DRCs
– The netlist is placed and routed (par) and a bitfile is generated
– The software device drivers are compiled into libraries
– The user application is compiled and linked against the libraries to created
an executable elf file
– Finally, the BRAMs in the bit file which comprise the program memory are
configured with the contents of the elf file
– Implementation/download.bit is the file to program the FPGA!