Digilent Memory Module 1 User Manual
Digilent Hardware
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w w w . d i g i l e n t i n c . c o m
Revision: 04/12/05
215 E Main Suite D | Pullman, WA 99163
(509) 334 6306 Voice and Fax
Doc: 502-033
page 1 of 3
Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners.
Overview
The Digilent Memory Module 1 circuit board
(the MEM1) is a byte wide memory board
containing static RAM memory and flash ROM
memory. It can be attached to a Digilent
system board to provide memory for use in
logic designs implemented on the system
board:
The MEM1 circuit board is available in various
memory configurations:
• C1: 512Kb SRAM, 512Kb Flash
• C2: 1Mb SRAM, no Flash
• C3: no SRAM, 1Mb Flash
Functional Description
The following is a brief description of the
operation of the memory devices on the MEM1
board. For complete documentation on the
operation of the various memory devices, refer
to the respective manufacturers data sheets.
The MEM1 board contains two memory banks,
Bank 0 and Bank 1. Bank 0 can be loaded with
either an ISSI IS63LV1024L-J 128K x 8 SRAM
or an ISSI IS61LV5128T 512K x 8 SRAM. Chip
select line CS0 enables the memory device
installed on Bank 0 for access.
Memory Bank 1 can be loaded with either an
ISSI IS61LV5128T 512K x 8 SRAM, a Micron
MT28F004B3 512K x 8 Flash ROM, or a
Micron MT28F008B3 1M x 8 Flash ROM. Chip
select line CS1 enables the memory device
installed on Bank 1 for access.
Configuration C1 has the IS61LV5128T
installed in Bank 0 and the MT28F004B3
installed in Bank 1.
Configuration C2 has the IS61LV5128T
installed in both Bank 0 and Bank 1.
Configuration C3 has the MT28F008B3 installed
in Bank1. Chip select line CS0 is used for the
highest-order address bit.
The MEM1 has 19 address inputs (A0-A18), 8 bi-
directional data input/outputs (D0-D7), two
chip/bank select inputs (CS0 and CS1), a single
read strobe input (OE) and a single write strobe
input (WE). Note: for the 128K IS64LV1024L-J
device, only address lines A0-A16 are used.
A memory read cycle is performed by placing the
address on the address lines, bringing the
appropriate chip select line low to enable the
memory device, bringing the OE line low and
then reading the data placed on the bi-directional
data lines by the selected memory device.
Connector J1
512K
RAM
128K
RAM
512K
RAM
512K
FLASH
Bank 0
Bank 1
OR
OR
MEM1 Circuit Diagram