Document Outline

• 1 INTRODUCTION
  • 1.1 USING THIS DOCUMENT
  • 1.2 RELATED DOCUMENTATION
  • 1.3 COMPATIBILITY STATEMENT
• 2 DESIGN GUIDE
  • 2.1 HARDWARE REQUIREMENTS
  • 2.2 SOFTWARE REQUIREMENTS
  • 2.3 SOFTWARE ARCHITECTURE
  • 2.4 UTILITIES
    • 2.4.1 D_MERGE
    • 2.4.2 CE_MERGE
• DESIGN REFERENCE
  • 3.1 PROGRAM MEMORY
  • 3.2 DATA MEMORY
  • 3.3 PROGRAMMING OF THE 71M652X CHIPS
  • 3.4 DEBUGGING OF THE 71M652X CHIPS
  • 3.5 TEST TOOLS
    • 3.5.1 Running the 652X_Demo.hex Program
    • 3.5.2 CLI Commands
    • 3.5.3 Command (Macro) Files
• TOOL INSTALLATION GUIDE
  • 4.1 INSTALLING THE PROGRAMS FOR THE ADM51 EMULATOR
  • 4.2 INSTALLING THE WEMU PROGRAM (CHAMELEON DEBUGGER)
  • 4.3 INSTALLING THE ADM51 USB DRIVER
  • 4.4 INSTALLING UPDATES TO THE EMULATOR PROGRAM AND HARDWARE
  • 4.5 CREATING A PROJECT
  • 4.6 INSTALLING THE KEIL COMPILER
  • 4.7 CREATING A PROJECT FOR THE KEIL COMPILER
    • 4.7.1 Directory Structure
    • 4.7.2 Adjusting the Keil Compiler Settings
    • 4.7.3 Manually Controlling the Keil Compiler Settings
  • 4.8 PROJECT MANAGEMENT TOOLS
  • 4.9 ALTERNATIVE COMPILERS
  • 4.10 ALTERNATIVE EDITORS
  • 4.11 ALTERNATIVE LINKERS
• DEMO CODE DESCRIPTION
  • 5.1 80515 DATA TYPES AND COMPILER-SPECIFIC INFORMATION
    • 5.1.1 Data Types
    • 5.1.2 Compiler-Specific Information
  • 5.2 DEMO CODE OPTIONS AND PROGRAM SIZE
  • 5.3 PROGRAM FLOW
    • 5.3.1 Startup and Initialization
  • 5.4 BASIC CODE ARCHITECTURE
    • 5.4.1 Initialization
    • 5.4.2 Foreground
      • Timer Interrupt
      • CE_BUSY Interrupt
      • XFER_BUSY and RTC Interrupt
      • 5.4.2.1 SERIAL Interrupt
    • 5.4.3 Background Tasks
      • meter_run()
      • meter_LCD
      • Command Line Interpreter
      • Auto-Calibration
      • CE Default Calibration
      • Command Pending
      • EEPROM Read/Write
      • Battery Test
      • Power Factor Measurement
    • 5.4.4 Watchdog Timer
    • 5.4.5 Real-Time Clock (RTC)
  • 5.5 MANAGING MISSION AND BATTERY MODES
  • 5.6 DATA FLOW
  • 5.7 CE/MPU INTERFACE
  • 5.8 BOOT LOADER
  • 5.9 SOURCE FILES
  • 5.10 AUXILIARY FILES
  • 5.11 INCLUDE/HEADER FILES
    • 5.11.1 OPTIONS.H
    • 5.11.2 Register Definitions
    • 5.11.3 Other Include/Header Files
  • 5.12 CE IMAGE FILES
  • 5.13 COMMON MPU ADDRESSES
  • 5.14 FIRMWARE APPLICATION INFORMATION
    • 5.14.1 Sag Detection
    • 5.14.2 Temperature Measurement
    • 5.14.3 Temperature Compensation for Measurements
    • 5.14.4 Temperature Compensation for the RTC
    • 5.14.5 Validating the Battery
  • 5.15 ALPHABETICAL FUNCTION REFERENCE
  • 5.16 ERRATA
  • 5.17 PORTING 71M6511/6513 CODE TO THE 71M6521
    • 5.17.1 Memory Use
    • 5.17.2 CE Code Location
    • 5.17.3 Battery Modes
    • 5.17.4 Three-Wire EEPROM Hardware
    • 5.17.5 Temperature Compensation
  • 5.18 TEST MODULES
    • 5.18.1 6513 CE Example
    • 5.18.2 Serial Port Tests
    • 5.18.3 Timer Tests
    • 5.18.4 EEPROM Tests
    • 5.18.5 Generating DIO Pulses on Reset
    • 5.18.6 Testing the Security Bit
    • 5.18.7 Software Timer Test
    • 5.18.8 Interrupt Test
• 80515 MPU REFERENCE
  • 6.1 80515 OVERVIEW
    • 6.1.1 80515 Performance
    • 6.1.2 80515 Features
  • 6.2 80515 ARCHITECTURAL OVERVIEW
    • 6.2.1 Memory organization
      • Program Memory
      • External Data Memory
      • Dual Data Pointer
      • Internal Data Memory
      • Special Function Registers Location
      • Generic Special Function Register Overview
      • Generic Special Function Registers Location and Reset Values
      • Special Function Registers Specific to the 652X
    • 6.2.2 The 80515 Instruction Set
      • Instructions Ordered by Function
      • Instructions Ordered by Opcode (Hexadecimal)
      • Instructions that Affect Flags
  • 6.3 80515 HARDWARE DESCRIPTION
    • 6.3.1 Block Diagram
    • 6.3.2 80515 MPU
      • Accumulator
      • The B Register
      • Program Status Word (PSW)
      • Stack Pointer
      • Data Pointer
      • Program Counter
      • Ports
      • Timers 0 and 1
      • Timer/Counter Mode Control Register (TMOD)
      • Timer/Counter Control Register (TCON)
      • 6.3.2.1 Allowed Combinations of Operation Modes
    • 6.3.3 Serial Interface 0 and 1
      • Serial Interface 0 Modes
      • Serial Interface 1 Modes
      • 6.3.3.1 Baud Rate generator
    • 6.3.4 Software Watchdog Timer
      • Software Watchdog Timer structure
      • 6.3.4.1 WD Timer Start Procedure
      • Refreshing the WD Timer
      • Special Function Registers for the WD Timer
        • Interrupt Enable 0 Register (IEN0):
        • Interrupt Enable 1 Register (IEN1):
        • Interrupt Priority 0 Register (IP0):
        • Watchdog Timer Reload Register (WDTREL):
    • 6.3.5 The Interrupt Service Routine Unit
      • 6.3.5.1 Interrupt Overview
      • 6.3.5.2 Special Function Registers for Interrupts
        • Interrupt Enable 0 Register (IE0)
        • Interrupt Enable 1 Register (IEN1)
        • Interrupt Enable 2 Register (IEN2)
        • Timer/Counter Control Register (TCON)
        • Interrupt Request Register (IRCON)
      • 6.3.5.3 External Interrupts
        • Interrupt Request register (T2CON)
      • 6.3.5.4 Interrupt Priority Level Structure
        • Interrupt Priority 0 Register (IP0)
        • Interrupt Priority 1 Register (IP1)
      • 6.3.5.5 Interrupt Sources and Vectors
        • External Interrupt Edge Detect
• APPENDIX
  • ACRONYMS
  • 7.2 REVISION HISTORY