Maxim Integrated MAXQ Family - Manual (Page 120)

11.7.4 SPI Data Buffer Register (SPIB)
Bits 15 to 0: SPI Data Buffer (SPIB.[15:0]). Data for SPI is read from or written to this location. The serial transmit and receive buffers
are separate but both are addressed at this location. Write access is allowed only outside of the transfer cycle. When the STBY bit is
set, write attempts are blocked and cause a write collision error.
11-8
MAXQ Family User’s Guide
Bit # 15 14 13 12 11 10 9 8
Name SPIB.15 SPIB.14 SPIB.13 SPIB.12 SPIB.11 SPIB.10 SPIB.9 SPIB.8
Reset 0 0 0 0 0 0 0 0
Access rs rs rs rs rs rs rs rs
Bit # 7 6 5 4 3 2 1 0
Name SPIB.7 SPIB.6 SPIB.5 SPIB.4 SPIB.3 SPIB.2 SPIB.1 SPIB.0
Reset 0 0 0 0 0 0 0 0
Access rs rs rs rs rs rs rs rs
r = read, s = special
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