Table 3-6. system register bit reset values -21, Maxq family user’s guide, Table 3-6. system register bit reset values – Maxim Integrated MAXQ Family User Manual
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Table 3-6. System Register Bit Reset Values
Note: Bits marked ‘s’ are static across some or all resets.
BIT POSITION
REGISTER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AP
0
0
0
0
0
0
0
0
APC
0
0
0
0
0
0
0
0
PSF
1
0
0
0
0
0
0
0
IC
0
0
0
0
0
0
0
0
IMR
0
0
0
0
0
0
0
0
SC
1
0
0
0
0
0
s
0
IIR
0
0
0
0
0
0
0
0
CKCN
s
s
s
0
0
0
0
0
WDCN
s
s
0
0
0
s
s
0
A[n]
MAXQ10
0
0
0
0
0
0
0
0
A[n]
MAXQ20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PFX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IP
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SP
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
IV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OFFS
0
0
0
0
0
0
0
0
DPC
MAXQ10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DPC
MAXQ20
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
GR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRL
0
0
0
0
0
0
0
0
BP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRH
0
0
0
0
0
0
0
0
GRXL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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