Z9973, Maximum ratings, Dc parameters – Cypress Z9973 User Manual
Page 6: Ac parameters
Z9973
Document #: 38-07089 Rev. *D
Page 6 of 9
Maximum Ratings
[3]
Maximum Input Voltage Relative to V
SS
: ............ V
SS
– 0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................–65
°
C to + 150
°
C
Operating Temperature: ................................ –40
°
C to +85
°
C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:
..................................................±
20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
(V
DD
= 2.9V to 3.6V, V
DDC
= 3.3V ±10%, T
A
= –40
°
C to +85
°
C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
IL
Input LOW Voltage
V
SS
0.8
V
V
IH
Input HIGH Voltage
2.0
V
DD
V
V
PP
Peak-to-Peak Input Voltage
PECL_CLK
300
1000
mV
V
CMR
Common Mode Range PECL_CLK
[9]
V
DD
– 2.0
V
DD
– 0.6
V
I
IL
Input Low Current
[10]
–120
µA
I
IH
Input High Current
[10]
120
µA
V
OL
Output Low Voltage
[11]
I
OL
= 20 mA
0.5
V
V
OH
Output High Voltage
[11]
I
OH
= –20 mA
2.4
V
I
DDQ
Quiescent Supply Current
10
15
mA
I
DDA
PLL Supply Current
V
DD
only
15
20
mA
I
DD
Dynamic Supply Current
QA and QB @ 60 MHz,
QC @ 120 MHz, C
L
= 30 pF
225
mA
QA and QB @ 25 MHz,
QC @ 50 MHz, C
L
= 30 pF
125
C
IN
Input Pin Capacitance
4
pF
AC Parameters
(V
DD
= 2.9V to 3.6V, V
DDC
= 3.3V ±10%, T
A
= –40
°
C to +85
°
C)
[4]
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
Tr / Tf
TCLK Input Rise / Fall
3.0
ns
Fref
Reference Input Frequency
Note 5
Note 5
MHz
FrefDC
Reference Input Duty Cycle
25
75
%
Fvco
PLL VCO Lock Range
200
480
MHz
Tlock
Maximum PLL Lock Time
10
ms
Tr / Tf
Output Clocks Rise/Fall Time
[6]
0.8V to 2.0V
0.15
1.2
ns
Notes:
3.
The voltage on any input or I/O pic cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
5.
Maximum and minimum input reference is limited by VC0 lock range.
6.
Outputs loaded with 30 pF each.