Document Outline

• Welcome
• Audience
• What’s New for Echelon’s Smart Transceivers and Neuron Chips
• Related Documentation
• Standards Documents Referenced in this Manual
• Table of Contents
• Introduction
  • Product Family Overview
    • FT 6000 Smart Transceiver
    • Neuron 6000 Processor
    • Development Resources for Series 6000 Chips
    • Introduction to LonWorks Networks
    • Overview of the IzoT Platform
    • Overview of Free Topology Technology
    • Key Features of Series 6000 Chips
      • Additional Key Features for FT 6000 Smart Transceivers
    • Specification Summaries
      • Specification Summary for FT 6000 Smart Transceivers
      • Specification Summary for Neuron 6000 Processors
• Hardware Resources
  • Series 6000 Architecture
    • Neuron Processor Architecture
    • Multiple Processors
    • Interrupts
    • Assembly Instruction Set
  • Memory Architecture
    • On-Chip Memory
    • Memory Map
    • External Serial Memory Interface
      • Serial Peripheral Interface (SPI)
      • Non-Volatile Memory Integrity
      • Device Support
      • Device Programming
      • Recovering a Device
    • Transience
    • Data Logging
    • Boot Loader
    • JTAG Interface
    • Operating Conditions
  • Pin Assignments
    • FT 6000 Smart Transceiver
    • Neuron 6000 Processor
  • Pin Connections
  • Characteristics of the Digital Pins
  • Communications Port (CP) Pins for the Neuron 6000 Processor
    • Single-Ended Mode
      • Collision Detection for Single-Ended Mode
      • Beta 1 and Beta 2 Timeslots in Single-Ended Mode
    • Special-Purpose Mode
  • Network Connection
    • Connection for an FT 6000 Smart Transceiver
      • Comparison with FT 3120 or FT 3150 Devices
      • Comparison with Series 5000 Devices
      • Comparison with the FTT-10A Transceiver
    • Connection for a Neuron 6000 Processor
  • Clock Requirements
    • External Crystal
    • Comparison with Series 3100 Clocks
  • Reset Function
    • RST~ Pin
    • Reset Sources
      • Power-Up and LVI
      • Watchdog Timer
      • Traps
      • Software-Controlled Reset
    • Reset Processes and Timing
  • SVC~ Pin
  • Integrity Mechanisms
    • Processor Integrity
    • System Firmware Image
    • Application Integrity Using Checksums
• Hardware Design Considerations
  • PC Board Layout Guidelines
• Design and Test for Electromagnetic Compatibility
  • Overview
  • Achieving High Immunity
  • Electrostatic Discharge
  • Electromagnetic Interference
  • Radiated and Conducted Immunity
  • Surge and Burst
  • Lightning Protection
    • Building Entrance Protection
    • Network Line Protection
    • Shield Protection
    • Suggested Gas Discharge Arresters
  • Avoiding Magnetic Field Interference
  • Summary and Testing Results
• Network Cabling and Connections for FT Devices
  • Network Connection
  • Network Topology Overview
  • System Performance and Cable Selection
    • System Specifications
    • Transmission Distance Specifications
  • Cable Termination and Shield Grounding
    • Free Topology Network Segment
    • Doubly Terminated Bus Topology Segment
    • Grounding Shielded Twisted Pair Cable
• Input/Output Interfaces for the Series 6000
  • Overview
  • Two 16-Bit Timer/Counters
  • Summary of the Available I/O Objects
  • Hardware Considerations
• Programming Considerations
  • Application Program Development
  • IzoT NodeBuilder Development Tool
    • Development Hardware Setup
    • Release Hardware Setup
    • SNMP Support
      • Supported Commands
      • Supported Objects
    • Migrating from earlier Neuron Chips
      • Migrating Self-Installation Routines
• Series 6000 Design Checklists
  • Checklist 1: Series 6000 Chip Connections
  • Checklist 2: FT 6000 Smart Transceiver Connections
  • Checklist 3: Neuron 6000 Processor Connections
  • Checklist 4: Power Supply
  • Checklist 5: Device PCB Layout
  • Checklist 6: Network Cabling and Termination
  • Checklist 7: Device Programming
• Qualified TP/FT-10 Cable Specifications
  • Introduction
  • Qualified Cables
    • Category 5 and 6 Cable Specifications
    • NEMA Type 4 Cable Specifications
    • 16 AWG (1.3 mm) “Generic” Cable Specifications
• FT-X3 Communications Transformer
  • Transformer Pinout
  • Transformer Electrical Connections
  • Transformer Pad Layout
• Handling and Manufacturing Guidelines
  • Application Considerations
    • Termination of Unused Pins
    • Avoidance of Damaging Conditions
    • Electrostatic Discharge Design Guidelines
    • Power Supply, Ground, and Noise Considerations
    • Decoupling Capacitors
  • Board Soldering Considerations
    • Recommended Solder Profile
    • Soldering Surface Mount (SMT) Parts
  • General ESD Handling Guidelines
  • Power Distribution and Decoupling Capacitors
  • Recommended Bypass Capacitor Placement
• Example Schematic
  • Example Schematic
    • Basic Electrical Connections
    • Memory Interface Connections
    • Transformer Connections
    • I/O and Network Connections
  • BOM for Example Schematic
• Vendor Contact Information
  • Vendor Information