Spectrum Controls 140 EHC 204 00sc - Manual (Page 37)

Quantum Series 140 EHC 204 00sc 140 EHC 208 00sc
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State, Bit 6”.
Zero
For the Counter
Indicates when the count is zero. The status of the flag is reflected in the counter zero bit in the 3X state register
register for the channel. See “ Counter Zero State, Bit 8”.
For the Input Rate
Indicates when the input rate is zero or below. The status of the flag is reflected in the rate zero bit in the 3X
state register register for the channel. See “ Rate Zero State, Bit 5”.
Setting bit 11 to 0 latches the normal state of the flags until they are reset. This allows the ladder logic program to monitor
the state of the flags and reset them (to 1) as needed when parameter settings change. Setting bit 11 to 1 reports the counter
flags to the PLC for one scan cycle, and then resets them automatically. If the maximum, limit, or zero condition still exists,
the module sets the flags back to 1 on the next update cycle.
NOTE: You can use bit 11 to reset the reset flags as a counter value passes through a maximum range value. However, the
two values cannot be equal at the time the counter value is read from the backplane. For example, if the counter limit is set
to 10,000, the counter limit flag is set when the count exceeds 10,000. The next count value transferred to the rack might be
10,050. The status register will have the counter maximum range flag set for this transfer of counter data.
Stop on Zero, Bit 10
Set this bit to 1 to hold the counter output at zero. When the counter counts down to zero, it
either rolls down through zero into full scale or holds its output at zero counts, until the counter zero
flag is reset. When the flag is reset, the counter continues to count. See “ Reset Flags, Bit 11.” for
more about the counter zero flag.
Stop on Limit, Bit 9
Set this bit to 1 to hold the counter output at its limit value. When the counter counts up to the
limit value, the counter either rolls over to zero or holds its output at the limit value, until the counter
limit flag is cleared. When the flag is cleared, the counter continues to count. If the user-defined
count limit is equal to zero, the limit is internally set to 65,536 (64 K count size) or 16,777,216 (16
M count size). See the count size parameter description in “ Making Bit Settings for Zoom Regis-
ters.”
Rate Mode, Bit 8
When this bit is reset to “0” the frequency detection circuit operates in “Instant” mode. Instant
mode times the period of a single input transition from one rising edge to the next rising edge of an
input signal. Instant measurements are fast, in that they calculate a frequency based on one cycle.
However the accuracy of the measurement degrades as the input clock frequency goes up to 50KHz,
and any jitter within one cycle will be measured.
When the frequency mode bit is set to a “1” the frequency detection circuit is in “Average”
mode. Average mode counts the number of input transitions over a 1 second interval and calculates
the input frequency averaged over the 1-second interval. The average mode is slow, in that it reports
updated frequency rates once per second. However this mode is accurate to +- 1 count over the full
range of measurement.