Altera Arria V Avalon-MM User Manual
Page 59
Table 4-16: PIPE Interface Signals
In the following table, signals that include lane number 0 also exist for other lanes.
Signal
Direction
Description
txdata0[7:0]
Output
Transmit data <n> (2 symbols on lane <n>). This bus transmits
data on lane <n>.
txdatak0
Output
Transmit data control <n>. This signal serves as the control bit
for
txdata
<n>.
txdetectrx0
Output
Transmit detect receive <n>. This signal tells the PHY layer to
start a receive detection operation or to begin loopback.
txelecidle0
Output
Transmit electrical idle <n>. This signal forces the TX output to
electrical idle.
txcompl0
Output
Transmit compliance <n>. This signal forces the running
disparity to negative in Compliance Mode (negative COM
character).
rxpolarity0
Output
Receive polarity <n>. This signal instructs the PHY layer to
invert the polarity of the 8B/10B receiver decoding block.
powerdown0[1:0]
Output
Power down <n>. This signal requests the PHY to change its
power state to the specified state (P0, P0s, P1, or P2).
tx_deemph0
Output
Transmit de-emphasis selection. The Arria V Hard IP for PCI
Express sets the value for this signal based on the indication
received from the other end of the link during the Training
Sequences (TS). You do not need to change this value.
rxdata0[7:0]
(1)
Input
Receive data <n> (2 symbols on lane <n>). This bus receives data
on lane <n>.
rxdatak0
(1)
Input
Receive data >n>. This bus receives data on lane <n>.
rxvalid0
(1)
Input
Receive valid <n>. This signal indicates symbol lock and valid
data on
rxdata
<n> and
rxdatak
<n>.
phystatus0
(1)
Input
PHY status <n>. This signal communicates completion of several
PHY requests.
UG-01105_avmm
2014.12.15
PIPE Interface Signals
4-29
Interfaces and Signal Descriptions
Altera Corporation