Altera LVDS SERDES Transmitter / Receiver User Manual
Features
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Table of contents
Document Outline
- LVDS SERDES Transmitter/Receiver IP Cores User Guide
- Features
- Installing and Licensing IP Cores
- Customizing and Generating IP Cores
- Upgrading IP Cores
- Parameter Settings
- Ports
- Prototypes and Component Declarations
- Functional Description
- Receiver Modes
- DPA PLL Calibration
- Initialization and Reset
- Source-Synchronous Timing Analysis and Timing Constraints
- Arria II GX, Arria V, Arria V GZ, Cyclone V, and Stratix V LVDS Package Skew Compensation Report Panel
- ALTLVDS IP Core in External PLL Mode
- Simulating Altera IP Cores in other EDA Tools
- Generating ALTLVDS IP Core Using Clear Box Generator
- Document Revision History