Altera 50G Interlaken MegaCore Function - Manual (Page 13)

If you select the Verilog HDL for synthesis and simulation models, the demonstration testbench and
example design files are located in <your_ip> _sim/ilk_core_50g/testbench .
Files Generated for Arria 10 Variations
The Quartus II software generates multiple files during generation of your 50G Interlaken IP core Arria
10 variation.
2-4 Files Generated for Arria 10 Variations
UG-01140
2015.05.04
Altera Corporation Getting Started With the 50G Interlaken IP Core
Send Feedback