Altera Arria V GX FPGA - Manual (Page 35)

Chapter 6: Board Test System 6–13
Using the Board Test System
July 2012 Altera Corporation Arria V GX FPGA Development Kit
User Guide
The SFP/SMA/C2C Tab
The SFP/SMA/C2C tab ( Figure 6–6 ) allows you to run test designs using the
transceivers and IO on FPGA 1.
The following sections describe the controls on the SFP/SMA/C2C tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Figure 6–6. The SFP/SMA/C2C Tab