Altera External Memory PHY Interface - Manual (Page 55)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–39
Additional Debug Signals
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
Additional Debug Signals
This section discusses the following debug signals:
■ “PLL and PLL Reconfiguration Signals”
■ “Calibration Status Interface”
■ “Additional Calibration Status Interface Signals”
PLL and PLL Reconfiguration Signals
Before any design operates correctly, all clock and reset signals must be stable and
configured correctly. Therefore, you must ensure that the various PLL ports are visible
in your simulation. This is of increased values when simulating a DDR and DDR2
SDRAM high-performance memory controller-based design because of the PLL phase
calibration stages that occur.
f For full description of each signal, refer to Phase-Locked Loop (ALTPLL) Megafunction
User Guide .
You must add the following ALTMEMPHY signals to your simulation:
■ seq_pll_select
■ phasecounterselect
■ seq_pll_inc_dec_n
■ phaseupdown
■ seq_pll_start_reconfig
■ configupdate
■ pll_reconfig_busy
■ pll_phase_done
■ pll_locked
■ phs_shft_busy
■ pll_reconfig_reset
In Arria GX, Stratix II, and Stratix II GX designs where a separate altpll_reconfig
instance is required, the following signals may be added to the simulation:
■ pll_reconfig
■ pll_reconfig_counter_param
■ pll_reconfig_counter_type
■ pll_reconfig_data_in
■ pll_reconfig_enable
■ pll_reconfig_read_param
■ pll_reconfig_soft_reset_en_n
■ pll_reconfig_write_param