Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 22)

2–14 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Arria II GX FPGA Development Board, 6G Edition Reference Manual © July 2010 Altera Corporation
Figure 2–5 shows the PFL configuration.
Figure 2–5. PFL Configuration
MAX II CPLD
EPM2210 System Controller
FPGA_DATA [7:0]
FPGA_DCLK
FLASH_A [25:1]
FLASH_D [15:0]
DATA [7:0]
DCLK
INIT_DONE
nSTATUS
nCONFIG
CONF_DONE
MSEL0
MSEL1
MSEL2
MSEL3
2.5 V
10 k Ω
nCE
CFI
Flash
10 k Ω
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [25:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RSTn
FLASH_ADVn
MSEL [3:0]
FPGA_nCONFIG
FPGA_CONF_DONE
FLASH_RYBSYn
FPGA_nSTATUS
2.5 V
10 k Ω
FLASH_ADVn
CONF_DONE_LED
2.5 V
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RSTn
FPP Port
Flash Interface
100 Ω
100 MHz
2.5 V
2.5 V
ERROR
MAX_LED
LOAD
DIP0
DIP1
DIP1
FACTORY/USER LOAD
LCD_PWRMON
USB_DISABLEn
CLK_EN
CLK_SEL
MAX_RESETn
LOAD_IMAGE
(RESET_CONF
IGN)
IMAGE_SEL
(FACTORY)
CONFIG_LED0
CONFIG_LED1
CONFIG_LED2
DIP Switch