Altera Cyclone V SoC Development Board - Manual (Page 20)

2–12 Chapter 2: Board Components
FPGA Configuration
Cyclone V SoC Development Board November 2013 Altera Corporation
Reference Manual
Figure 2–3 illustrates the JTAG chain.
The JTAG chain control DIP switch (SW4) controls the jumpers shown in Figure 2–3 .
To connect a device or interface to the chain, their corresponding switch must be in
the OFF position. Slide all the switches in the ON position to only have the FPGA in
the chain.
1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some
of the GUI interfaces.
Figure 2–3. JTAG Chain
1
1
1
1
Disable
Trace TCK TMS
TDI
TDO
TRST
Cypress On-Board
USB-Blaster II
TCK TMS
TDI
TDO
10-Pin
JTAG Header
TCK TMS
TDI
TDO
TRST
Mictor-38
Header
TCK
TMS
TDI
TDO
TRST
Cyclone V SX HPS
TCK
TMS
TDI
TDO
TRST
Cyclone V SX SoC
TCK
TMS
TDI
TDO
HSMC Port A
TCK
TMS
TDI
TDO
5M2210 System
Controller
Flash
Memory