Altera Stratix IV E FPGA Development Board - Manual (Page 64)

2–56 Chapter 2: Board Components
Memory
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Table 2–51 lists the flash pin assignments, signal names, and functions.
Table 2–51. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference
Description
Schematic Signal Name
I/O
Standard
Stratix IV E
Device
Pin Number
Other
Connections
U2.F6 Address valid FLASH_ADVn
2.5-V
D20 U10.L13
U2.B4 Chip enable FLASH_CEn K25 U10.K14
U2.E6 Clock FLASH_CLK K24 U10.L15
U2.F8 Output enable FLASH_OEn K23 U10.M16
U2.F7 Ready FLASH_RDYBSYn C20 U10.L11
U2.D4 Reset FLASH_RESETn G21 U10.M15
U2.G8 Write enable FLASH_WEn L22 U10.L12
U2.C6 Write protect FLASH_WPn — —
U2.A1 Address bus FSM_A1 H23 U10.T8
U2.B1 Address bus FSM_A2 G23 U10.T9, U3.R6
U2.C1 Address bus FSM_A3 F23 U10.R9, U3.P6
U2.D1 Address bus FSM_A4 D27 U10.P9, U3.A2
U2.D2 Address bus FSM_A5 D28 U10.T10, U3.A10
U2.A2 Address bus FSM_A6 F25 U10.P13, U3.B2
U2.C2 Address bus FSM_A7 F26 U10.R10, U3.B10
U2.A3 Address bus FSM_A8 G24 U10.M10, U3.N6
U2.B3 Address bus FSM_A9 F24 U10.T11, U3.P3
U2.C3 Address bus FSM_A10 E26 U10.N10, U3.P4
U2.D3 Address bus FSM_A11 D26 U10.R11, U3.P8
U2.C4 Address bus FSM_A12 A30 U10.P10, U3.P9
U2.A5 Address bus FSM_A13 A33 U10.T12, U3.P10
U2.B5 Address bus FSM_A14 B31 U10.M11, U3.P11
U2.C5 Address bus FSM_A15 A31 U10.R12, U3.R3
U2.D7 Address bus FSM_A16 B32 U10.N11, U3.R4
U2.D8 Address bus FSM_A17 A32 U10.T13, U3.R8
U2.A7 Address bus FSM_A18 M23 U10.P11, U3.R9
U2.B7 Address bus FSM_A19 L23 U10.R13, U3.R10
U2.C7 Address bus FSM_A20 B29 U10.M12, U3.R11
U2.C8 Address bus FSM_A21 C29 U10.R14, U3.B1
U2.A8 Address bus FSM_A22 C31 U10.N12, U3.A1
U2.G1 Address bus FSM_A23 D31 U10.T15, U3.B11
U2.H8 Address bus FSM_A24 F27 U10.P12, U3.C10
U2.B6 Address bus FSM_A25 D18 U10.E13, U3.P2
U2.B8 Address bus FSM_A26 W10 U10.J16
U2.F2 Data bus FSM_D0 G27 U10.P4, U3.J10