Altera Arria V GT FPGA Development Board - Manual (Page 6)

1–2 Chapter 1: Overview
Board Component Blocks
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
Board Component Blocks
The development board features the following major component blocks:
■ Two Arria V GT FPGA 5AGTFD7K3F40I3N in the 1517-pin FineLine BGA (FBGA)
package
■ 504K LEs
■ 190,240 adaptive logic modules (ALMs)
■ 24,140 Kbit (Kb) M10K on-die memory
■ 2,906 Kb MLAB memory
■ 36 transceivers
■ 16 phase locked loops (PLLs)
■ 2,312 18x18 multipliers
■ 1.15-V core voltage
■ MAX ® II CPLD EPM2210GF324 System Controller in the 324-pin FBGA package
■ FPGA configuration circuitry
■ MAX II CPLD EPM570GM100 and flash fast passive parallel (FPP)
configuration
■ On-board USB-Blaster TM II for use with the Quartus ® II Programmer
■ Clocking circuitry
■ Nine on-board oscillators
■ One 50-MHz oscillator
■ Two 125-MHz oscillators
■ Clock buffer with six outputs sourced by SMA or programmable oscillator
with a default frequency of 100-MHz
■ One programmable oscillator with a default frequency of 148.5-MHz
■ Four programmable oscillators with four outputs each of various default
frequencies
■ Clock buffer with two outputs sourced by one of the above four
programmable oscillators with one output to the FPGA reference clock and
Bull's Eye
® SMA
■ SMA connectors for external LVPECL clock input
■ Power supply
■ 14-V – 20-V DC input
■ PCI Express edge connector power
■ 12-V PCI Express ATX supply
■ On-board power measurement circuitry