Altera Cyclone III Development Board - Manual (Page 7)

Chapter 1: Overview 1–3
General Description
© March 2009 Altera Corporation Cyclone III 3C120 Development Board Reference Manual
■ FPGA configuration circuitry
■ MAX II CPLD and flash passive serial configuration
■ On-board USB-Blaster™ circuitry using the Quartus II Programmer
■ On-board clocking circuitry
■ Two clock oscillators to support Cyclone III device user logic
■ 50 MHz
■ 125 MHz
■ 80 I/O, 6 clocks, SMBus, and JTAG
■ SMA connector for external clock input and output
■ General user and configuration interfaces
■ LEDs/displays:
■ Eight user LEDs
■ One transmit/receive LED (TX/RX) per HSMC interface
■ One configuration done LED
■ Ethernet LEDs
■ User 7-segment display
■ Power consumption display
■ Memory activity LEDs:
■ SRAM
■ FLASH
■ DDR2 Top
■ DDR2 Bottom
■ Push-buttons:
■ One user reset push-button (CPU reset)
■ Four general user push-buttons
■ One system reset push-button (user configuration)
■ One factory push-button switch (factory configuration)
■ DIP switches:
■ One MAX control DIP switch
■ One JTAG control switch
■ Eight user DIP switches
■ Speaker header
■ Displays
■ 128 × 64 graphics LCD
■ 16 × 2 line character LCD