BECKHOFF ET1100 - Manual (Page 43)

EtherCAT IP Core for Xilinx FPGAs
Slave Controller – Application Note FAQ 39
5.3.4 General timing closure issues
Regarding constraints, we can only give general advice on increasing the synthesis effort. The default
synthesis and implementation features are a good starting point, the following additional options might
increase timing closure:
XST – Synthesis Options
Optimization Goal = Speed
Optimization Effort = High
XST – Xilinx Specific Options
Register Duplication = On
Equivalent Register Removal = Off
Map Properties
Perform Timing-Driven Packing and Placement = On
Map Effort = Standard (or even High or High + Extra Effort)
Combinatorial Logic Optimization = On
Register Duplication = On
Allow Logic Optimization Across Hierarchy = On
Optimization Strategy (Cover Mode) = Speed
Place & Route Properties
Place & Route Effort Level (Overall) = High (or even Extra Effort = Normal)
General advice
Over-constraining was not found useful with current synthesis, it might cause the tools to put too much
effort in paths which would originally pass, and consequently making other paths slower.
Find out if the violating path consists basically of logic or routing delays. If the logic delays are too
high, reduce the number of features, increase optimization effort, or use a faster speed grade.
Generally, the more features are used, the tighter becomes the timing. Especially 64 bit Distributed
Clocks are very demanding, due to the high register count. The low-cost FPGAs are often not able to
use 64 bit DC at all. In many cases using 32 bit DC solves the problem.
If many FPGA resources are available, the design is sometimes spread widely across the FPGA,
resulting in long connections with high routing delay. Reduce the available FPGA resources/area for
the EtherCAT IP Core to improve timing.
Generally, it is impossible to predict timing closure for custom user logic in combination with all IP
Core configurations and FPGA devices. Final certainty can only be reached by implementing the
design
– that is what the evaluation versions are for. There will be combinations which are not able to
reach timing closure at all.