Measurement Computing CIO-PDMAxx - Manual (Page 10)

4.2 SIGNAL FUNCTIONAL DESCRIPTIONS
Positive or negative edge triggered input. Software
programmable. INTERRUPT
A low on this signal will hold the gates of 8254
counter 0 and counter 1 low, thereby inhibiting inputs
to the counters. This signal is pulled up by a 10K
resitor to +5V. TIMER GATE
Output from 8254 counter 1. TIMER OUT
This line goes low upon receipt of a TRANSFER
ACK. OUT then returns high after the DMA transfer
has completed. At that point, the transfer has taken
place and if it was an output, is valid to be read from
port(s) A (and B). TRANSFER ACK. OUT
Positive edge initiates a DMA transfer if DMA is
enabled and bit 3 of the DMA control register = 0. TRANSFER REQ IN
Output only. 0 = input, 1 = output PORT B DIR. OUT
Output only. 0 = input, 1 = output PORT A DIR. OUT
Output-only digital lines. AUX DIG 1- 3
Port B input/output lines. B0 = LSB PORT B0 - B7
Port A input/output lines. A0 = LSB PORT A0 - A7
4.3 DIGITAL OUTPUTS & INPUTS
All the digital inputs/outputs on the CIO-PDMA board are at TTL level. TTL is an
electronics industry term, short for Transistor-Transistor-Logic, which describes a
standard for digital signals which are either at 0V or 5V (nominal).
Under normal operating conditions, the voltages on Port A or Port B pins range from
0 to 0.45 volts for the low (0) state to between 2.4 to 5.0 volts for the high (1) state.
At 0.45 volts, a port can safely sink 24 mA. At 2.4 volts, a port can source 2.6 mA.
These values are typical of TTL devices.
4.4 TERMINATING DIGITAL LINES
When transferring digital data at high rates over cables, the impedance of the cable
and both ends should be matched as closely as possible to avoid “ringing” or
reflections in the line. To accomplish this, it may be necessary to add resistors in
series with the data lines at the source of the signals.
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