Grass Valley 8950DAC - Manual (Page 42)

42 8950DAC Instruction Manual
Functional Description
Serial Input and Deserializer
The serial input and deserializer are a standard chip set for receiving and
converting a D1 serial digital video stream into the 10-bit parallel 601
digital video signal. This section regenerates a 27 MHz clock from the
incoming serial data stream.
Phase Lock Loop (PLL) 2 Times Clock Generator
From the incoming 27 MHz clock, the PLL generates a 54 MHz clock used
for 4 times oversampling. This clock also servers as a free-running clock
when no input signal is present.
Digital to Analog Converter (DAC)
This board has four 10-bit high speed DACs producing Y/G, B-Y/B,
R-Y/R and analog Composite Sync outputs.
Output Low Pass Filters (LPF) and Buffers
After the DACs, the video signal passes through Low Pass Filters (4 per
board) and finally through the output amplifiers/buffers to the output
BNCs. Additional slow, I2C, 8x DAC provides the calibration and user
control for the output signal level and output black level.
Delay Line
On board delay line provides an additional 2.5 lines signal delay. The delay
time is under user control with the 37 ns step.
Embedded Processor
The embedded processor provides the interface between user and all the
processing logic inside the 8950DAC, as well as communication between a
remote host processor and the 8950DAC.