Figure3.5 lvd receiver, Table 3.9 diffsens scsi signal, Table 3.10 input capacitance – Avago Technologies LSI53C180 User Manual
Page 44: Lvd receiver, Diffsens scsi signal, Input capacitance
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3-10
Specifications
Figure 3.5
LVD Receiver
Table 3.9
DIFFSENS SCSI Signal
Symbol Parameter
Min
Max
Units
Test
Conditions
1
1. Functional test specified for each mode (V
S
and V
IL
).
V
S
LVD sense voltage
0.7
1.9
V
Note 1
V
IL
Single-ended sense
voltage
V
SS
−
0.3
0.5
V
Note 1
I
OZ
3-state leakage
−
10
10
µ
A
V
PIN
= 0 V, 5.25 V
Table 3.10
Input Capacitance
Symbol
Parameter
Min
Max
Units
Test
Conditions
C
I
Input capacitance of input pads
–
7
pF
–
C
IO
Input capacitance of I/O pads
–
10
pF
–
V
CM
+
−
+
+
+
−
−
−
V
I
2
V
I
2
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