Avago Technologies ACPL-7210-00RE User Manual

User guide, Evbd-acsl-7210 profibus / spi evaluation board, Product description

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EVBD-ACSL-7210 PROFIBUS / SPI Evaluation Board

ACSL-7210 Dual-Channel (Bidirectional) 25 MBd
CMOS Buffered Input Digital Optocoupler

User Guide

Product Description

Avago’s ACSL-7210 optocoupler utilizes the latest CMOS

IC technology to achieve outstanding speed and low

power performance of minimum 25 MBd data rate.
Available in SO-8 package, the basic building blocks of

each channel in ACSL-7210 are a CMOS LED driver IC, a

high speed LED and a CMOS detector IC. A CMOS logic

input signal controls the LED driver IC, which supplies cur-

rent to the LED. The detector IC incorporates an integrated

photodiode, a high speed trans-impedance amplifier, and

a voltage comparator with an output driver.

Functional Diagram

Features

• Dual-Channel (Opposite direction orientation)
• 3.3 V and 5 V CMOS Compatibility
• High Speed: DC to 25 MBd
• CMOS output and buffer input
• Operating temperature: –40°C to +105°C
• Safety and Regulatory Approvals:

- UL 1577 – 3750 Vrms for 1 minute
- IEC/EN/DIN EN 60747-5-5

About the Evaluation Board

The ACSL-7210 PROFIBUS / SPI evaluation board is con-

figurable for either PROFIBUS (RS-485) or SPI communica-

tion. The board will accept both 3.3V and 5V power sup-

plies.
When configured for PROFIBUS communication, the

ACSL-7210 bi-directional optocoupler provides isolation

for both the transmitting and receiving channels. Isolation

for the Tx Enable signal is provided by the ACPL-M61L, ul-

tra low power 10MBd CMOS digital optocoupler. A stan-

dard RS-485 transceiver (max. data rate of 20Mbps) is in-

cluded on the board.
For SPI interface, the ACSL-7210 is used for serial data in/

out isolation. Isolation for the clock signal is provided by

ACPL-077L, low power 25MBd CMOS digital optocoupler.
Figures 1 and 2 shows the jumper settings for PROFIBUS

and SPI operation. Figure 3 shows the schematic diagram

of the evaluation board.

ACSL-7210

8

5

6

VO

A

VDD

2

GND

2

VO

B

Shield

1

VDD

1

GND

1

4

7 VI

A

VI

B

3

2

TRUTH TABLE (POSITIVE LOGIC)

Input side

V

DD

state

Output side

V

DD

state

V

I

LED

V

O

Power

Supplied

Power

Supplied

HIGH

OFF

HIGH

LOW

ON

LOW

No Power

Power

Supplied

X

OFF

HIGH

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