Document Outline

• JESD204B IP Core User Guide
• Contents
• 1. JESD204B IP Core Quick Reference
• 2. About the JESD204B IP Core
  • Datapath Modes
  • IP Core Variation
  • JESD204B IP Core Configuration
    • Run-Time Configuration
  • Channel Bonding
  • Performance and Resource Utilization
• 3. Getting Started
  • Introduction to Altera IP Cores
  • Installing and Licensing IP Cores
  • Upgrading IP Cores
  • IP Catalog and Parameter Editor
  • Design Walkthrough
    • Creating a New Quartus II Project
    • Parameterizing and Generating the IP Core
    • Generating and Simulating the IP Core Testbench
      • Generating the Testbench Simulation Model
      • Simulating the IP Core Testbench
    • Compiling the JESD204B IP Core Design
    • Programming an FPGA Device
  • JESD204B IP Core Design Considerations
    • Integrating the JESD204B IP core in Qsys
    • Pin Assignments
    • Adding External Transceiver PLL
    • Timing Constraints For Input Clocks
  • JESD204B IP Core Parameters
  • JESD204B IP Core Component Files
  • JESD204B IP Core Testbench
    • Testbench Simulation Flow
• 4. JESD204B IP Core Functional Description
  • Transmitter
    • TX Data Link Layer
      • TX CGS
      • TX ILAS
      • User Data Phase
    • TX PHY Layer
  • Receiver
    • RX Data Link Layer
      • RX CGS
      • Frame Synchronization
      • Frame Alignment
      • Lane Alignment
      • ILAS Data
      • Initial Lane Synchronization
    • RX PHY Layer
  • Operation
    • Operating Modes
    • Scrambler/Descrambler
    • SYNC_N Signal
    • Link Reinitialization
    • Link Startup Sequence
    • Error Reporting Through SYNC_N Signal
  • Clocking Scheme
    • Device Clock
    • Link Clock
    • Local Multi-Frame Clock
    • Clock Correlation
  • Reset Scheme
    • Reset Sequence
  • Signals
    • Transmitter
    • Receiver
  • Registers
    • Register Access Type Convention
• 5. JESD204B IP Core Design Guidelines
  • JESD204B IP Core Design Example
    • Design Example Components
      • PLL
      • PLL Reconfiguration
      • Transceiver Reconfiguration Controller
      • Transceiver Reset Controller
      • Pattern Generator
        • Parallel PRBS Generator
        • Alternate Checkerboard Generator
        • Ramp Wave Generator
      • Pattern Checker
        • Parallel PRBS Checker
        • Alternate Checkerboard Checker
        • Ramp Wave Checker
      • Transport Layer
        • Supported System Configuration
          • Dynamic Downscaling Of System Parameters (L, N, and F)
          • Relationship Between Frame Clock and Link Clock
        • Data Bit and Content Mapping Scheme
        • TX Path
          • TX Path Operation
          • TX Data Transmission
          • TX Path Data Remapping
          • TX Error Reporting
          • TX Latency
        • RX Path
          • RX Path Operation
          • RX Data Reception
          • RX Path Data Remapping
          • RX Error Reporting
          • RX Latency
      • Serial Port Interface (SPI)
      • Control Unit
        • Memory Block (ROM)
        • Finite State Machine (FSM)
    • System Parameters
      • Run-Time Reconfiguration
    • System Interface Signals
    • Example Feature: Dynamic Reconfiguration
      • Dynamic Reconfiguration Operation
      • MIF ROM
    • Generating and Simulating the Design Example
      • Generating the Design Example Simulation Model
      • Simulating the JESD204B IP Core Design Example
    • Generating the Design Example For Compilation
    • Compiling the JESD204B IP Core Design Example
• 6. JESD204B IP Core Deterministic Latency Implementation Guidelines
  • Constraining Incoming SYSREF Signal
  • Programmable RBD Offset
  • Programmable LMFC Offset
• 7. JESD204B IP Core Debug Guidelines
  • Clocking Scheme
  • JESD204B Parameters
  • SPI Programming
  • Converter and FPGA Operating Conditions
  • Signal Polarity and FPGA Pin Assignment
  • Debugging JESD204B Link Using SignalTap II and System Console
• 8. Additional Information
  • JESD204B IP Core Document Revision History
  • How to Contact Altera