Document Outline

• MAX 10 Clocking and PLL User Guide
• Contents
• 1. MAX 10 Clocking and PLL Overview
  • Clock Networks Overview
  • Internal Oscillator Overview
  • PLLs Overview
• 2. MAX 10 Clocking and PLL Architecture and Features
  • Clock Networks Architecture and Features
    • Global Clock Networks
    • Clock Pins Introduction
    • Clock Resources
    • Global Clock Network Sources
    • Global Clock Control Block
    • Global Clock Network Power Down
    • Clock Enable Signals
  • Internal Oscillator Architecture and Features
  • PLLs Architecture and Features
    • PLL Architecture
    • PLL Features
    • PLL Locations
    • Clock Pin to PLL Connections
    • PLL Counter to GCLK Connections
    • PLL Control Signals
    • Clock Feedback Modes
      • Source Synchronous Mode
      • No Compensation Mode
      • Normal Mode
      • Zero-Delay Buffer Mode
    • PLL External Clock Output
    • ADC Clock Input from PLL
    • Spread-Spectrum Clocking
    • PLL Programmable Parameters
      • Programmable Duty Cycle
      • Programmable Bandwidth
      • Programmable Phase Shift
    • Clock Switchover
      • Automatic Clock Switchover
      • Automatic Switchover with Manual Override
      • Manual Clock Switchover
    • PLL Cascading
      • PLL-to-PLL Cascading
      • Counter-to-Counter Cascading
    • PLL Reconfiguration
• 3. MAX 10 Clocking and PLL Design Considerations
  • Clock Networks Design Considerations
    • Guideline: Clock Enable Signals
    • Guideline: Connectivity Restrictions
  • Internal Oscillator Design Considerations
    • Guideline: Connectivity Restrictions
  • PLLs Design Considerations
    • Guideline: PLL Control Signals
    • Guideline: Self-Reset
    • Guideline: Output Clocks
    • Guideline: PLL Cascading
    • Guideline: Clock Switchover
    • Guideline: .mif Streaming in PLL Reconfiguration
    • Guideline: scandone Signal for PLL Reconfiguration
• 4. MAX 10 Clocking and PLL Implementation Guides
  • ALTCLKCTRL IP Core
    • IP Catalog and Parameter Editor
    • Specifying IP Core Parameters and Options
    • Files Generated for Altera IP Cores (Legacy Parameter Editor)
  • ALTPLL IP Core
    • IP Catalog and Parameter Editor
    • Specifying IP Core Parameters and Options
      • Expanding the PLL Lock Range
      • Programmable Bandwidth with Advanced Parameters
      • PLL Dynamic Reconfiguration Implementation
        • Post-Scale Counters (C0 to C4)
        • Scan Chain
        • Charge Pump and Loop Filter
        • Bypassing PLL Counter
      • Dynamic Phase Configuration Implementation
        • Dynamic Phase Configuration Counter Selection
        • Dynamic Phase Configuration with Advanced Parameters
    • Files Generated for Altera IP Cores (Legacy Parameter Editor)
  • ALTPLL_RECONFIG IP Core
    • IP Catalog and Parameter Editor
    • Specifying IP Core Parameters and Options
    • Files Generated for Altera IP Cores (Legacy Parameter Editor)
    • Obtaining the Resource Utilization Report
  • Internal Oscillator IP Core
    • IP Catalog and Parameter Editor
    • Specifying IP Core Parameters and Options
    • Files Generated for Altera IP Cores (Legacy Parameter Editor)
• 5. ALTCLKCTRL IP Core References
  • ALTCLKCTRL Parameters
  • ALTCLKCTRL Ports and Signals
• 6. ALTPLL IP Core References
  • ALTPLL Parameters
    • Operation Modes Parameter Settings
    • PLL Control Signals Parameter Settings
    • Programmable Bandwidth Parameter Settings
    • Clock Switchover Parameter Settings
    • PLL Dynamic Reconfiguration Parameter Settings
    • Dynamic Phase Configuration Parameter Settings
    • Output Clocks Parameter Settings
  • ALTPLL Ports and Signals
• 7. ALTPLL_RECONFIG IP Core References
  • ALTPLL_RECONFIG Parameters
  • ALTPLL_RECONFIG Ports and Signals
  • ALTPLL_RECONFIG Counter Settings
• 8. Internal Oscillator IP Core References
  • Internal Oscillator Parameters
  • Internal Oscillator Ports and Signals
• A. Additonal Information for MAX 10 Clocking and PLL User Guide
  • Document Revision History for MAX 10 Clocking and PLL User Guide