Avago Technologies LSI53C825AE Instruction Manuals and User Guides
We have 2 Instruction Manuals and User Guides for LSI53C825AE Avago Technologies
Manuals
| Recognized languages: | English |
|---|---|
| Pages: | 322 |
| Size: | 2.57 MB |
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Document Outline
- SCSI SCRIPTS™ Processors
- Chapter1 Using the Programming Guide
- Chapter2 Programming with SCRIPTS
- Chapter3 The SCSI SCRIPTS Processor Instruction Set
- 3.1 Overview of SCRIPTS Instructions
- 3.2 Instruction Descriptions
- Table 3.3 SCRIPTS Instructions Set
- 3.2.1 CALL
- 3.2.2 CHMOV
- 3.2.3 CLEAR
- 3.2.4 DISCONNECT
- 3.2.5 INT
- 3.2.6 INTFLY
- 3.2.7 JUMP
- 3.2.8 JUMP 64
- 3.2.9 LOAD
- 3.2.10 LOAD64
- 3.2.11 MOVE
- 3.2.12 MOVE MEMORY
- 3.2.13 MOVE REGISTER
- 3.2.14 NOP
- 3.2.15 RESELECT
- 3.2.16 RETURN
- 3.2.17 SELECT
- 3.2.18 SET
- 3.2.19 STORE
- 3.2.20 WAIT DISCONNECT
- 3.2.21 WAIT SELECT
- 3.2.22 WAIT RESELECT
- 3.3 Instruction Examples
- Chapter4 Using the LSI Logic Assembler NASM™
- Chapter5 The NASM Output File
- Chapter6 Using the Registers to Control Chip Operations
- Chapter7 Integrating SCRIPTS Programs into “C” Language Drivers
- Chapter8 Writing Device Drivers with SCRIPTS
- Chapter9 SCRIPTS Programming Topics
- 9.1 Scatter/Gather Operations
- 9.2 Loopback Mode
- 9.3 Byte Recovery on Target Disconnect
- 9.4 Synchronous Negotiation and Transfer
- 9.5 Interrupt Handling
- 9.6 Migrating Existing Software to Ultra, Ultra2, and Ultra3 SCSI
- 9.7 Using the SCRIPTS RAM
- Chapter10 Multithreaded I/O
- 10.1 Overview
- 10.2 Multithreaded Operations Flow
- 10.3 SCRIPTS Areas
- 10.4 Multithreaded SCRIPTS Example
- Figure10.3 Multithreaded SCRIPTS Example Step 1
- Figure10.4 Multithreaded SCRIPTS Example Step 2
- Figure10.5 Multithreaded SCRIPTS Example Step 3
- Figure10.6 Multithreaded SCRIPTS Example Step 6
- Figure10.7 Multithreaded SCRIPTS Example Step 10
- Figure10.8 Multithreaded SCRIPTS Example Step 11
- Figure10.9 Multithreaded SCRIPTS Example Step 13
- 10.5 Using the SIGP Bit to Abort an Instruction
- 10.6 I/O Completion
- Chapter11 Using the SCRIPTS Processor in Target Applications
- 11.1 SCSI and Target SCRIPTS Protocol
- 11.2 Registers Used for Target Operation
- 11.3 Using SCRIPTS for Target Operation
- 11.3.1 Sample Target Operation SCRIPTS Program
- Figure11.1 SCRIPTS Source Code–Comments
- Figure11.2 SCRIPTS Source Code–ABSOLUTE Declarations
- Figure11.3 SCRIPTS Source Code–EXTERN Variables
- Figure11.4 SCRIPTS Source Code–TABLE
- Figure11.5 SCRIPTS Source Code–ENTRY Declarations
- Figure11.6 SCRIPTS Source Code–wait_select Label
- Figure11.7 SCRIPTS Source Code–CDB Functions
- Figure11.8 SCRIPTS Source Code–Message Out Phase
- Figure11.9 SCRIPTS Source Code–Extended Message
- Figure11.10 SCRIPTS Source Code–Synchronous Negotiation
- Figure11.11 SCRIPTS Source Code–Wide Negotiation
- Figure11.12 SCRIPTS Source Code–Return Negotiation
- Figure11.13 SCRIPTS Source Code–Recovery Message
- Figure11.14 SCRIPTS Source Code–Test Unit Ready
- Figure11.15 SCRIPTS Source Code–stopped_busy_tur Command
- Figure11.16 SCRIPTS Source Code–Request Sense
- Figure11.17 SCRIPTS Source Code–Read Label
- Figure11.18 SCRIPTS Source Code–read_disconnect Label
- Figure11.19 SCRIPTS Source Code–read_reconnect Label
- Figure11.20 SCRIPTS Source Code–Write
- Figure11.21 SCRIPTS Source Code–write_disconnect Label
- Figure11.22 SCRIPTS Source Code–write_reconnect Label
- Figure11.23 SCRIPTS Source Code–reserve_unit Label
- Figure11.24 SCRIPTS Source Code–release_unit Command
- Figure11.25 SCRIPTS Source Code–abort Label
- Figure11.26 SCRIPTS Source Code–stopped_busy_wait_select Command
- 11.3.1 Sample Target Operation SCRIPTS Program
- 11.4 Synchronous Negotiation by a Target Device
- Chapter12 Debugging the SCRIPTS Processor
- Chapter13 New SCRIPTS Processor Features
- 13.1 Improved FIFO Flushing
- 13.2 Larger FIFO
- 13.3 New ISTAT Registers
- 13.4 New Scratch Registers
- 13.5 New Load/Store Feature
- 13.6 Phase Mismatch Handling
- 13.7 64-Bit SCRIPTS Addressing
- AppendixA NASM Error Messages
- AppendixB Multithreaded SCRIPTS Example
- AppendixC Glossary of Terms and Abbreviations
- Index
- Customer Feedback
| Recognized languages: | English |
|---|---|
| Pages: | 306 |
| Size: | 1.22 MB |
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Document Outline
- LSI53C825A/825AE PCI to SCSI I/O Processor
- Chapter1 Introduction
- Chapter2 Functional Description
- 2.1 PCI Addressing
- 2.2 SCSI Functional Description
- 2.3 External Memory Interface
- 2.4 PCI Cache Mode
- 2.4.1 Load and Store Instructions
- 2.4.2 3.3 V/5 V PCI Interface
- 2.4.3 Additional Access to General Purpose Pins
- 2.4.4 JTAG Boundary Scan Testing
- 2.4.5 Big and Little Endian Support
- 2.4.6 Loopback Mode
- 2.4.7 Parity Options
- 2.4.8 DMA FIFO
- 2.4.9 SCSI Bus Interface
- 2.4.10 Select/Reselect During Selection/Reselection
- 2.4.11 Synchronous Operation
- 2.4.12 Achieving Optimal SCSI Send Rates
- 2.4.13 Interrupt Handling
- 2.4.14 Chained Block Moves
- 2.5 Power Management
- Chapter3 Signal Descriptions
- Figure3.1 LSI53C825A Pin Diagram
- Figure3.2 LSI53C825AJ Pin Diagram
- Table 3.1 LSI53C825A, LSI53C825AJ, LSI53C825AE, and LSI53C825AJE Power and Ground Pins
- Figure3.3 LSI53C825A Functional Signal Grouping
- 3.1 PCI Bus Interface Signals
- 3.2 MAD Bus Programming
- Chapter4 Registers
- 4.1 Configuration Registers
- 4.2 Operating Registers
- Table 4.2 LSI53C825A Register Map
- Table 4.3 Synchronous Clock Conversion Factor
- Table 4.4 Examples of Synchronous Transfer Periods and Rates for SCSI-1
- Table 4.5 Example Transfer Periods and Rates for Fast SCSI-2
- Table 4.6 Maximum Synchronous Offset
- Table 4.7 Timeout Periods
- Table 4.8 Timeout Periods, 50 MHz Clock
- Chapter5 SCSI SCRIPTS Instruction Set
- Chapter6 Specifications
- 6.1 DC Characteristics
- Table 6.1 Absolute Maximum Stress Ratings
- Table 6.2 Operating Conditions
- Table 6.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
- Table 6.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
- Table 6.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS, BIG_LIT/
- Table 6.6 Capacitance
- Table 6.7 Output Signals—MAC/_TESTOUT, REQ/
- Table 6.8 Output Signals—IRQ/, SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/...
- Table 6.9 Output Signal—SERR/
- Table 6.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...
- Table 6.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4
- Table 6.12 Bidirectional Signals—MAD[7:0]
- Table 6.13 Input Signals—TDI, TMS, TCK (LSI53C825AJ only)
- Table 6.14 Output Signal—TDO (LSI53C825AJ only)
- 6.2 TolerANT Technology Electrical Characteristics
- 6.3 AC Characteristics
- 6.4 PCI and External Memory Interface Timing Diagrams
- 6.4.1 Target Timing
- 6.4.2 Initiator Timing
- 6.4.3 External Memory Timing
- Figure6.21 Read Cycle, Normal/Fast Memory (³ 64 Kbytes), Single Byte Access
- Figure6.22 Write Cycle, Normal/Fast Memory (³ 64 Kbytes), Single Byte Access
- Figure6.23 Read Cycle, Normal/Fast Memory (³ 64 Kbytes), Multiple Byte Access
- Figure6.24 Write Cycle, Normal/Fast Memory (³ 64 Kbytes), Multiple Byte Access
- Figure6.25 Read Cycle, Slow Memory (³ 64 Kbytes)
- Figure6.26 Write Cycle, Slow Memory (³ 64 Kbytes)
- Figure6.27 Read Cycle, Normal/Fast Memory (³ 64 Kbytes)
- Figure6.28 Write Cycle, Normal/Fast Memory (³ 64 Kbytes)
- Figure6.29 Read Cycle, Slow Memory (£ 64 Kbytes)
- Figure6.30 Write Cycle, Slow Memory (£ 64 Kbytes)
- 6.5 PCI and External Memory Interface Timing
- 6.6 SCSI Timing Diagrams
- Table 6.20 Initiator Asynchronous Send
- Figure6.31 Initiator Asynchronous Send
- Table 6.21 Initiator Asynchronous Receive
- Figure6.32 Initiator Asynchronous Receive
- Table 6.22 Target Asynchronous Send
- Figure6.33 Target Asynchronous Send
- Table 6.23 Target Asynchronous Receive
- Figure6.34 Target Asynchronous Receive
- Figure6.35 Initiator and Target Synchronous Transfers
- Table 6.24 SCSI-1 Transfers (SE 5.0 Mbytes)
- Table 6.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s)
- Table 6.26 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transf...
- Table 6.27 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfers...
- 6.7 Package Drawings
- 6.1 DC Characteristics
- AppendixA Register Summary
- AppendixB External Memory Interface Diagram Examples
- Index
- Customer Feedback