Document Outline

• 1. Features
  • 1.1 Applications
• 2. Logic Block Diagram
• 3. Introduction
• 4. Conventions
• 5. Pinouts
• 6. CPU Architecture
• 7. CPU Registers
  • 7.1 Flags Register
  • 7.2 Addressing Modes
    • 7.2.1 Source Immediate
    • 7.2.2 Source Direct
    • 7.2.3 Source Indexed
    • 7.2.4 Destination Direct
    • 7.2.5 Destination Indexed
    • 7.2.6 Destination Direct Source Immediate
    • 7.2.7 Destination Indexed Source Immediate
    • 7.2.8 Destination Direct Source Direct
    • 7.2.9 Source Indirect Post Increment
    • 7.2.10 Destination Indirect Post Increment
• 8. Instruction Set Summary
• 9. Memory Organization
  • 9.1 Flash Program Memory Organization
  • 9.2 Data Memory Organization
  • 9.3 Flash
    • 9.3.1 Flash Programming and Security
    • 9.3.2 In System Programming
  • 9.4 SROM
    • 9.4.1 Return Codes
  • 9.5 SROM Function Descriptions
    • 9.5.1 SWBootReset Function
    • 9.5.2 ReadBlock Function
    • 9.5.3 WriteBlock Function
    • 9.5.4 EraseBlock Function
    • 9.5.5 ProtectBlock Function
    • 9.5.6 EraseAll Function
    • 9.5.7 TableRead Function
    • 9.5.8 Checksum Function
• 10. Clocking
  • 10.1 Clock Architecture Description
    • 10.1.1 Interval Timer Clock (ITMRCLK)
    • 10.1.2 Timer Capture Clock (TCAPCLK)
  • 10.2 CPU Clock During Sleep Mode
• 11. Reset
  • 11.1 Power on Reset
  • 11.2 Watchdog Timer Reset
• 12. Sleep Mode
  • 12.1 Sleep Sequence
  • 12.2 Wake up Sequence
  • 12.3 Low Power in Sleep Mode
• 13. Low Voltage Detect Control
  • 13.0.1 ECO Trim Register
• 14. General Purpose IO (GPIO) Ports
  • 14.1 Port Data Registers
  • 14.2 GPIO Port Configuration
    • 14.2.1 Int Enable
    • 14.2.2 Int Act Low
    • 14.2.3 TTL Thresh
    • 14.2.4 High Sink
    • 14.2.5 Open Drain
    • 14.2.6 Pull up Enable
    • 14.2.7 Output Enable
    • 14.2.8 VREG Output/SPI Use
    • 14.2.9 3.3V Drive
• 15. Serial Peripheral Interface (SPI)
  • 15.1 SPI Data Register
  • 15.2 SPI Configure Register
  • 15.3 SPI Interface Pins
• 16. Timer Registers
  • 16.1 Registers
    • 16.1.1 Free Running Counter
    • 16.1.2 Timer Capture
• 17. Interrupt Controller
  • 17.1 Architectural Description
  • 17.2 Interrupt Processing
  • 17.3 Interrupt Trigger Conditions
  • 17.4 Interrupt Latency
  • 17.5 Interrupt Registers
    • 17.5.1 Interrupt Mask Registers
• 18. Regulator Output
  • 18.1 VREG Control
• 19. USB/PS2 Transceiver
  • 19.1 USB Transceiver Configuration
• 20. USB Serial Interface Engine (SIE)
• 21. USB Device
  • 21.1 USB Device Address
  • 21.2 Endpoint 0, 1, and 2 Count
  • 21.3 Endpoint 0 Mode
  • 21.4 Endpoint 1 and 2 Mode
• 22. USB Mode Tables
  • 22.1 Mode Column
  • 22.2 Encoding Column
  • 22.3 SETUP, IN, and OUT Columns
• 23. Details of Mode for Differing Traffic Conditions
• 24. Register Summary
• 25. Voltage Vs CPU Frequency Characteristics
• 26. Absolute Maximum Ratings
• 27. DC Characteristics
• 28. AC Characteristics
• 29. Ordering Information
• 30. Package Handling
• 31. Package Diagrams
• 32. Document History Page
• 33. Sales, Solutions, and Legal Information
  • Worldwide Sales and Design Support
  • Products
  • PSoC Solutions