Document Outline

• Intel® IQ80219 General Purpose PCI Processor Evaluation Platform
• Introduction 1
  • 1.1 Document Purpose and Scope
  • 1.2 Related Documents
    • Table 1. Intel® 80219 General Purpose PCI Processor Related Documentation List
  • 1.3 Electronic Information
    • Table 2. Electronic Information
  • 1.4 Component References
    • Table 3. Component Reference
  • 1.5 Terms and Definitions
    • Table 4. Terms and Definitions
  • 1.6 Intel® 80219 General Purpose PCI Processor
    • Figure 1. Intel® 80219 General Purpose PCI Processor Block Diagram
  • 1.7 Intel® IQ80219 Evaluation Platform Board Features
    • Table 5. Summary of Features
• Getting Started 2
  • 2.1 Kit Content
  • 2.2 Hardware Installation
    • 2.2.1 First-Time Installation and Test
    • 2.2.2 Power and Backplane Requirements
  • 2.3 Factory Settings
  • 2.4 Development Strategy
    • 2.4.1 Supported Tool Buckets
    • 2.4.2 Contents of the Flash
  • 2.5 Target Monitors
    • 2.5.1 Redhat Redboot
    • 2.5.2 ARM Firmware Suite
      • 2.5.2.1 ARM Angel
        • 2.5.2.1.1 Semihosting (File I/O)
  • 2.6 Host Communications Examples
    • 2.6.1 Serial-UART Communication
      • Figure 2. Serial-UART Communication
    • 2.6.2 Ethernet-Network Communication
      • Figure 3. Ethernet-Network Communication
    • 2.6.3 JTAG Debug Communication
      • Figure 4. JTAG Debug Communication
    • 2.6.4 GNUPro GDB/Insight
      • 2.6.4.1 Communicating with Redboot
      • 2.6.4.2 Connecting with GDB
    • 2.6.5 ARM Extended Debugger
• Hardware Reference Section 3
  • 3.1 Functional Diagram
    • Figure 5. Functional Block Diagram
  • 3.2 Board Form-Factor/Connectivity
    • Table 6. Form-Factor/Connectivity Features
    • Figure 6. Board Form Factor
  • 3.3 Power
    • Table 7. Power Features
  • 3.4 Memory Subsystem
    • 3.4.1 DDR SDRAM
      • Table 8. DDR Memory Features
      • Table 9. Supported DIMM Types
      • 3.4.1.1 Battery Backup
    • 3.4.2 Flash Memory Requirements
      • Table 10. Flash Memory Requirements
  • 3.5 Intel® 80219 General Purpose PCI Processor Operation Mode
  • 3.6 Interrupt Routing
    • Figure 7. External Interrupt Routing to Intel® 80219 General Purpose PCI Processor
  • 3.7 Intel® IQ80219 Evaluation Platform Board Peripheral Bus
    • Figure 8. Intel® IQ80219 Evaluation Platform Board Peripheral Bus Topology
    • Table 11. Peripheral Bus Features
    • 3.7.1 Flash ROM
      • Table 12. Flash ROM Features
      • Figure 9. Flash Connection on Peripheral Bus
    • 3.7.2 UART
      • Table 13. UART Features
      • Figure 10. UART Connection on the Peripheral Bus
    • 3.7.3 HEX Display
      • Table 14. HEX Display on the Peripheral Bus
      • Figure 11. HEX Display Connection on the Peripheral Bus
    • 3.7.4 Rotary Switch
      • Table 15. Rotary Switch Requirements
      • Figure 12. Rotary Switch Connection on the Peripheral Bus
    • 3.7.5 Battery Status
      • Table 16. Battery Status Buffer Requirements
      • Figure 13. Battery Status Buffer on Peripheral Bus
  • 3.8 Debug Interface
    • 3.8.1 Console Serial Port
    • 3.8.2 Ethernet Port
      • 3.8.2.1 Intel® 82544EI Gigabit Ethernet Controller
    • 3.8.3 JTAG Debug
      • 3.8.3.1 JTAG Port
        • Figure 14. JTAG Port Pin-out
    • 3.8.4 Logic-Analyzer Connectors
      • Table 17. Logic Analyzer Connection
    • 3.8.5 Mictor J3F2
      • Table 18. Micor J3F2 Signal/Pins
    • 3.8.6 Mictor J2F1
      • Table 19. Micor J2F1 Signal/Pins
    • 3.8.7 Mictor J1C1
      • Table 20. Micor J1C1 Signal/Pins
    • 3.8.8 Mictor J3C1
      • Table 21. Micor J3C1 Signal/Pins
    • 3.8.9 Mictor J2C1
      • Table 22. Micor J2C1 Signal/Pins
  • 3.9 Board Reset Scheme
    • Table 23. Reset Requirements/Schemes
    • Figure 15. RESET Sources
  • 3.10 Switches and Jumpers
    • 3.10.1 Switch Summary
      • Table 24. Switch Summary
    • 3.10.2 PCIX Initialization Summary
      • Figure 16. PCI-X Routing Diagram on Secondary PCI-X Bridge
      • 3.10.2.1 User Defined Switches
      • 3.10.2.2 PCI-X Bridge Initialization Signals
    • 3.10.3 Default Switch Settings - Visual
      • Table 25. Switch S7E1
      • Table 26. Switch S8E1
      • Table 27. Switch S8E2
      • Table 28. Switch S9E1
      • Table 29. Switch S1D1
      • Table 30. Switch S4D1
    • 3.10.4 Jumper Summary
      • Table 31. Jumper Summary
    • 3.10.5 Connector Summary
      • Table 32. Connector Summary
    • 3.10.6 General Purpose Input/Output Header
      • Table 33. GPIO Header (J3F1) Definition
    • 3.10.7 Secondary PCI/PCI-X Operation Settings
      • Table 34. Secondary PCI/PCI-X Operation Settings
    • 3.10.8 Primary PCI/PCI-X Operation Settings
      • Table 35. Primary PCI/PCI-X Operation Settings
    • 3.10.9 Detail Descriptions of Switches/Jumpers
      • 3.10.9.1 Switch S7E1- 2/3
        • Table 36. Switch S7E1- 2/3: General Descriptions
        • 3.10.9.1.1 S7E1-2: RST_MODE
          • Table 37. Switch S7E1-2: RST_MODE: Settings and Operation Mode
        • 3.10.9.1.2 S7E1-3: RETRY
          • Table 38. Switch S7E1-3: RETRY: Settings and Operation Mode
        • 3.10.9.1.3 Operation Setting Summary Descriptions
          • Table 39. RST_MODE and RETRY Operation Setting Summary
      • 3.10.9.2 Switch S7E1- 4/5
        • Table 40. Switch S7E1 - 4/5: Descriptions
        • 3.10.9.2.1 Switch S7E1 - 4
          • Table 41. Switch S7E1 - 4: Settings and Operation Mode
        • 3.10.9.2.2 Switch S7E1 - 5
          • Table 42. Switch S7E1 - 5: Settings and Operation Mode
      • 3.10.9.3 Switch S7E1- 6/7
        • Table 43. Switch S7E1 - 6/7: Descriptions
        • Table 44. Switch S7E1 - 6/7: Settings and Operation Mode
      • 3.10.9.4 Switch S7E1- 8
        • Table 45. Switch S7E1 - 8: Descriptions
        • Table 46. Switch S7E1 - 8: Settings and Operation Mode
      • 3.10.9.5 Switch S8E1- 2
        • Table 47. Switch S8E1 - 2: Descriptions
        • Table 48. Switch S8E1 - 2: Settings and Operation Mode
      • 3.10.9.6 Switch S8E1- 3
        • Table 49. Switch S8E1 - 3: Descriptions
        • Table 50. Switch S8E1 - 3: Settings and Operation Mode
      • 3.10.9.7 Switch S8E1- 4
        • Table 51. Switch S8E1 - 4: Descriptions
        • Table 52. Switch S8E1 - 4: Settings and Operation Mode
      • 3.10.9.8 Switch S8E1- 5
        • 3.10.9.8.1 Switch S8E1 - 5: Descriptions
          • Table 53. Switch S8E1 - 5: Settings and Operation Mode
          • Table 54. Switch S8E1 - 5: Driver Mode Output Impedances
      • 3.10.9.9 Switch S8E1- 6
        • Table 55. Switch S8E1 - 6: Descriptions
        • Table 56. Switch S8E1 - 6: Settings and Operation Mode
        • Table 57. Switch S8E1 - 6: Driver Mode Output Impedances
      • 3.10.9.10 Switch S8E1- 7
        • Table 58. Switch S8E1 - 7: Descriptions
        • Table 59. Switch S8E1 - 7: Settings and Operation Mode
      • 3.10.9.11 Switch S8E1- 8
        • Table 60. Switch S8E1 - 8: Descriptions
        • Table 61. Switch S8E1 - 8: Settings and Operation Mode
      • 3.10.9.12 Switch S8E2 - 1/2
        • Table 62. Switch S8E2 - 1/2: Descriptions
        • Table 63. Switch S8E2 - 1/2: Settings and Operation Mode
      • 3.10.9.13 Switch S8E2 - 4
        • Table 64. Switch S8E2 - 4: Descriptions
        • Table 65. Switch S8E2 - 4: Settings and Operation Mode
      • 3.10.9.14 Switch S9E1 - 1:3
        • Table 66. Switch S9E1 - (1:3) Descriptions
        • Table 67. Switch S9E1 - (1:3) Settings and Operation Mode
      • 3.10.9.15 Switch S9E1 - 4
        • Table 68. Switch S9E1 - 4: Descriptions
        • Table 69. Switch S9E1 - 4: Settings and Operation Mode
      • 3.10.9.16 Switch S1D1 - 1/2
        • Table 70. Switch S1D1 - 1/2: Descriptions
        • Table 71. Switch S1D1 - 1/2: Settings and Operation Mode
      • 3.10.9.17 Switch S4D1 - 1/2
        • Table 72. Switch S4D1 - 1/2: Descriptions
        • Table 73. Switch S4D1 - 1/2: Settings and Operation Mode
      • 3.10.9.18 Switch S4D1 - 3/4
        • Table 74. Switch S4D1 - 3/4: Descriptions
        • Table 75. Switch S4D1 - 3/4: Settings and Operation Mode
      • 3.10.9.19 Jumper J1G2
        • Table 76. Jumper J1G2: Descriptions
        • Table 77. Jumper J1G2: Settings and Operation Mode
      • 3.10.9.20 Jumper J3E1
        • Table 78. Jumper J3E1: Descriptions
        • Table 79. Jumper J3E1: Settings and Operation Mode
      • 3.10.9.21 Jumper J3G1
        • Table 80. Jumper J3G1: Descriptions
        • Table 81. Jumper J3G1: Settings and Operation Mode
      • 3.10.9.22 Jumper J9E1
        • Table 82. Jumper J9E1: Descriptions
        • Table 83. Jumper J9E1: Settings and Operation Mode
      • 3.10.9.23 Jumper J9F1
        • Table 84. Jumper J9F1: Descriptions
        • Table 85. Jumper J9F1: Settings and Operation Mode
• External RAID Section 4
  • 4.1 Private Device Configuration
    • Table 86. Private Device Configuration Requirements
    • Figure 17. IDSEL Routing for Private Device Configuration
  • 4.2 Interrupt Routing
    • Table 87. Interrupt Routing for Secondary PCI-X Private Device
    • Figure 18. Interrupt Routing for Private Device Configuration
• Software Reference 5
  • 5.1 DRAM
    • Table 88. DDR Memory Bias Voltage Minimum/Maximum Values
  • 5.2 Components on the Peripheral Bus
    • 5.2.1 Flash ROM
      • Figure 19. Flash Connection to Peripheral Bus
    • 5.2.2 UART
      • Figure 20. UART Connection to Peripheral Bus
      • Table 89. UART Register Settings
    • 5.2.3 Rotary Switch
    • 5.2.4 HEX Display
      • Figure 21. Hex Display Connection to Peripheral Bus
      • Figure 22. 7-Segment Display Bit Definition
      • Figure 23. Register Bitmap: 7-Segment Display MSB FE84 0000h (Write Only)
      • Figure 24. Register Bitmap: 7-Segment Display LSB FE85 0000h (Write Only)
  • 5.3 Ethernet
  • 5.4 Board Support Package (BSP) Examples
    • 5.4.1 Intel® 80219 General Purpose PCI Processor Memory Map
      • Figure 25. Intel® 80219 General Purpose PCI Processor Memory Map
    • 5.4.2 Redboot* Intel® IQ80219 Memory Map
    • 5.4.3 Redboot Intel® IQ80219 Physical Memory Map - Visual
      • Figure 26. Redboot Intel® IQ80310 Physical Memory Map
    • 5.4.4 Redboot Intel® IQ80219 Virtual Memory Map - Visual
      • Figure 27. Redboot Intel® IQ80310 Virtual Memory Map
    • 5.4.5 Redboot Intel® IQ80219 Files
    • 5.4.6 Redboot Intel® IQ80219 DDR Memory Initialization Sequence
    • 5.4.7 Redboot Switching
• IQ80310 and IQ80219 Comparisons A
  • Table 90. Intel® IQ80310 and Intel® IQ80219 evaluation platform board Comparisons
• Getting Started and Debugger B
  • B.1 Introduction
    • B.1.1 Purpose
    • B.1.2 Necessary Hardware and Software
    • B.1.3 Related Documents
      • Table 91. Related Documents
    • B.1.4 Related Web Sites
  • B.2 Setup
    • B.2.1 Hardware Setup
      • Figure 28. Intel® IQ80219 Hardware Setup Flow Chart
    • B.2.2 Software Setup
      • Figure 29. Software Flow Diagram
  • B.3 New Project Setup
    • B.3.1 Creating a New Project
    • B.3.2 Configuration
  • B.4 Flashing with JTAG
    • B.4.1 Overview
    • B.4.2 Using Flash Programmer
  • B.5 Debugging Out of Flash
  • B.6 Building an Executable File From Example Code
  • B.7 Running the Code|Lab Debugger
    • B.7.1 Launching and Configuring Debugger
    • B.7.2 Manually Loading and Executing an Application Program
    • B.7.3 Displaying Source Code
    • B.7.4 Using Breakpoints
    • B.7.5 Stepping Through the Code
    • B.7.6 Setting Code|Lab Debug Options
  • B.8 Exploring the Code|Lab Debug Windows
    • B.8.1 Toolbar Icons
    • B.8.2 Workspace Window
    • B.8.3 Source Code
    • B.8.4 Debug and Console Windows
    • B.8.5 Memory Window
    • B.8.6 Registers Window
    • B.8.7 Watch Window
    • B.8.8 Variables Window
  • B.9 Debugging Basics
    • B.9.1 Overview
    • B.9.2 Hardware and Software Breakpoints
      • B.9.2.1 Software Breakpoints
      • B.9.2.2 Hardware Breakpoints
    • B.9.3 Exceptions/Trapping
• Getting Started and Debugger C
  • C.1 Introduction
    • C.1.1 Purpose
    • C.1.2 Necessary Hardware and Software
    • C.1.3 Related Documents
      • Table 92. Related Documents
    • C.1.4 Related Web Sites
  • C.2 Setup
    • C.2.1 Hardware Setup
      • Figure 30. Intel® IQ80219 Hardware Setup Flow Chart
    • C.2.2 Software Setup
      • Figure 31. Software Flow Diagram
  • C.3 New Project Setup
    • C.3.1 Creating a New Project
    • C.3.2 Configuration
  • C.4 Flashing with JTAG
    • C.4.1 Overview
    • C.4.2 Using Flash Programmer
  • C.5 Debugging Out of Flash
  • C.6 Building an Executable File From Example Code
  • C.7 Running the Code|Lab Debugger
    • C.7.1 Launching and Configuring Debugger
    • C.7.2 Manually Loading and Executing an Application Program
    • C.7.3 Displaying Source Code
    • C.7.4 Using Breakpoints
    • C.7.5 Stepping Through the Code
    • C.7.6 Setting Code|Lab Debug Options
  • C.8 Exploring the Code|Lab Debug Windows
    • C.8.1 Toolbar Icons
    • C.8.2 Workspace Window
    • C.8.3 Source Code
    • C.8.4 4 Debug and Console Windows
    • C.8.5 Memory Window
    • C.8.6 Registers Window
    • C.8.7 Watch Window
    • C.8.8 Variables Window
  • C.9 Debugging Basics
    • C.9.1 Overview
    • C.9.2 Hardware and Software Breakpoints
      • C.9.2.1 Software Breakpoints
      • C.9.2.2 Hardware Breakpoints
    • C.9.3 C.9.3 Exceptions/Trapping