Document Outline

• Contents
• List of Figures
• List of Tables
• List of Examples
• Using This Guide
  • Purpose
  • Audience
  • Byte Ordering and Bit Coding Convention
  • Type Definition
  • Code Examples
  • Icon Conventions
  • Text Conventions
  • Checking and Downloading from the Interphase WWW/FTP Site
    • WWW Method
    • FTP Method
• Hardware Description
  • Overview
    • 4538 Hardware Structure
  • The PowerQUICC II
    • PowerQUICC II Resets
    • System Clocks
    • PCI Local Space Mapping
    • Interrupts
    • Memory Controllers
    • Communication Processor Module (CPM) I/O Ports
    • CPM TDM Busses
    • Bank of Clocks
    • Baud Rate Generator
    • Ethernet 10/100BaseT
    • TTY Console Serial Port
    • User-Programmable LEDs
  • The PCI Bridge
    • PowerSpan PCI Configuration Registers
    • PowerSpan PCI Registers
    • PowerSpan Processor Bus Registers
    • PowerSpan DMA Registers
    • PowerSpan Miscellaneous Registers
    • PowerSpan I·O Registers
    • Interrupt Pins and Doorbell Usage
    • PCI to Local Interrupt (ATN)
    • Local to PCI Interrupt (–INTA)
    • Hardware and Software Resets Through the PowerSpan
    • Local Space Access From PCI Memory Space
    • Access to the FLASH EEPROM Through CompactPCI
    • PCI Memory Space and I/O Space Access From the PowerQUICC II
    • In-situ EPLDs Programming
    • Serial EEPROM Connected to the PowerSpan
    • Board Equipment Register
    • Vital Product Data (VPD)
    • Interphase-Specific Production Data and Boot Monitor Parameters
  • The FLASH EEPROM Boot Memory
  • The QuadFALC T1/E1/J1 Framer
  • The Ethernet Transceiver
  • TDM Bus Configurations
    • General
    • Multiplex Direct Mode
    • Independent Direct Mode
    • Switched Mode
    • Pass-Through Mode
• 4538 Power-Up Initialization
  • Overview
  • PowerSpan Initialization
    • PowerSpan Hardware Configuration Word
    • PowerSpan Register Initialization Through the I·C Serial EEPROM
    • Other PowerSpan Initializations
  • PowerQUICC II Hardware Configuration Word
  • PowerQUICC II Initializations
    • PowerQUICC II System Interface Unit (SIU) Initialization
      • Internal Memory Map Register (IMMR)
      • Bus Configuration Register (BCR)
      • System Protection Control Register (SYPCR)
      • 60x Bus Arbiter Registers (PPC_ACR, PPC_ALRH, and PPC_ALRL)
      • SIU Module Configuration Register (SIUMCR)
      • Bus Transfer Error Registers (TESCR1 and L_TESCR1)
    • Memory Controllers
      • SDRAM Controller and SDRAM Device Initialization
      • GPCM Controller Initialization
      • UPM Controller Programming
    • MPC603e Core Initialization
      • MMU Initialization
      • Cache Initialization
    • Communication Processor Module Initialization
      • I/O Port Initialization
      • CPM RCCR Reset
• Programming the Peripherals
  • Overview
  • PowerQUICC II CPM Initialization
    • Serial Interfaces and Time Slot Assigner Initialization
      • TDM Busses in Multiplexed Direct Mode and in Switched Mode
      • TDM Busses in Independent Direct Mode
      • TDM Busses in Pass-Through Mode
    • Clocks and Baud-Rate Generators
      • Introduction
      • BRGCLK
      • BRG7 – TTY Baud-Rate Generator
    • MCC Initialization
  • T1/E1/J1 Framer Initialization
    • Introduction
    • Master Clock Initialization
    • TDM Busses General Structure
      • Multiplexed Direct Mode
      • Independent Direct Mode
      • Switched Mode
      • Pass-Through Mode
    • Framing and Line Coding Initialization
      • Common Initialization
      • T1 Specific Initialization
      • E1/E1-CRC4 Common Initialization
      • E1 Non-CRC4 Specific Initialization
      • E1-CRC4 Specific Initialization
      • Clock Synchronization Initialization
    • Transmit Pulse Shape
    • Line LED Control
  • The Ethernet Port Initialization
  • The TTY Framer Initialization
• Accessing the 4538 on the PCI Side
  • PowerSpan Configuration by the PCI Host
    • PCI Configuration
    • Interrupt Pin Configuration
    • PCI-to-Local Window Configuration
  • Controlling the 4538 Hardware and Software Resets
  • Controlling the PCI-to-Local Interrupt
  • Local to PCI Interrupt (–INTA)
  • Local Space Access From PCI Memory Space
  • Access to the FLASH EEPROM Through PCI
    • FLASH EEPROM Programming Algorithms
  • Serial EEPROM Connected to the PowerSpan
  • In Situ EPLD Programming
  • Optimizing the PCI Bus Utilization
  • Effective Ordering of the PCI Accesses
  • PCI Deadlock Situations
• Connectors and Front Panel
  • Connector Placement
  • Front Panel
    • LED Descriptions
    • RJ48 Connectors J1 and J2
    • Ethernet 10/100 RJ45 Connector J3
    • TTY Serial Port J4
  • PMC Connectors
    • PMC Connectors P1 and P2
    • PMC Connector P4
  • Debug Port J5
  • ISP Enable Jumper JP1
  • Blank Card Jumper JP2
  • Connector Summary
  • Carrier Card Specification
    • CompactPCI Carrier Card
    • Custom Carrier Card
  • 6435 Rear Transition Module
• Mechanical Information
  • PMC Card Dimensions
  • Carrier Card Dimension Requirements
• Bibliography
  • Industry Standards
  • Telecommunication Standards
  • Manufacturers’ Documents
• Glossary
• Index