Document Outline

• Features
• 1. Pinout and Schematic
  • 1.1 Pinout Configuration
  • 1.2 Pin Descriptions
  • 1.3 Schematics
• 2. Overview of the AT42QT1110
  • 2.1 Introduction
  • 2.2 Configurations
  • 2.3 Guard Channel
  • 2.4 Self-test Functions
• 3. Wiring and Parts
  • 3.1 Cs Sample Capacitors
  • 3.2 Rs Resistors
  • 3.3 LED Traces and Other Switching Signals
  • 3.4 PCB Cleanliness
  • 3.5 Power Supply
    • 3.5.1 General Considerations
    • 3.5.2 Brownout Detection
  • 3.6 MLF Package Restrictions
• 4. Detailed Operations
  • 4.1 Communications
    • 4.1.1 Introduction
    • 4.1.2 SPI Operation
    • 4.1.3 CRC Bytes
    • 4.1.4 SPI Commands
      • 4.1.4.1 Control Commands
    • 4.1.5 Report Requests
      • 4.1.5.1 Set Instructions
      • 4.1.5.2 Get Instructions
    • 4.1.6 Quick SPI Mode
      • 4.1.6.1 Introduction
      • 4.1.6.2 Quick SPI Report
      • 4.1.6.3 Commands in Quick SPI Mode
      • 4.1.6.4 Quick SPI Mode timing
  • 4.2 Reset
  • 4.3 Sleep Mode
  • 4.4 Calibration
  • 4.5 CHANGE Pin
  • 4.6 Stand-alone Mode
  • 4.7 Key Modes
    • 4.7.1 11-key Mode
    • 4.7.2 7-key Mode
  • 4.8 Trigger Modes
    • 4.8.1 Timed Trigger
    • 4.8.2 Synchronized Trigger
  • 4.9 Guard Channel Option
  • 4.10 Self-test Functions
    • 4.10.1 Internal Hardware Tests
    • 4.10.2 Functional Checks
  • 4.11 Signal Processing
    • 4.11.1 Detection Integrator
    • 4.11.2 Burst Length Limitations
    • 4.11.3 Adjacent Key Suppression Technology
• 5. Control Commands
  • 5.1 Introduction
  • 5.2 Send Setups (0x01)
  • 5.3 Calibrate All (0x03)
  • 5.4 Reset (0x04)
  • 5.5 Sleep (0x05)
  • 5.6 Store to EEPROM (0x0A)
  • 5.7 Restore from EEPROM (0x0B)
  • 5.8 Erase EEPROM (0x0C)
  • 5.9 Recover EEPROM (0x0D)
  • 5.10 Calibrate Key (0x1k)
• 6. Report Requests
  • 6.1 Introduction
  • 6.2 First Key (0xC0)
  • 6.3 All Keys (0xC1)
  • 6.4 Device Status (0xC2)
  • 6.5 EEPROM CRC (0xC3)
  • 6.6 RAM CRC (0xC4)
  • 6.7 Error Keys (0xC5)
  • 6.8 Signal for Key “k” (0x2k)
  • 6.9 Reference for Key “k” (0x4k)
  • 6.10 Status for Key “k” (0x8k)
  • 6.11 Detect Output States (0xC6)
  • 6.12 Last Command (0xC7)
  • 6.13 Setups (0xC8)
  • 6.14 Device ID (0xC9)
  • 6.15 Firmware Version (0xCA)
• 7. Setups and Status Information
  • 7.1 Introduction
  • 7.2 Setting Individual Settings
  • 7.3 Setting All the Setups
  • 7.4 Address 0: Device Mode
  • 7.5 Address 1: Guard Key/Comms Options
  • 7.6 Address 2: Detect Integrator Limit (DIL)/Drift Hold Time (DHT)
  • 7.7 Address 3: Positive Threshold (PTHR)/Positive Hysteresis (PHYST)
  • 7.8 Address 4: Positive Drift Compensation (PDRIFT)
  • 7.9 Address 5: Positive Recalibration Delay (PRD)
  • 7.10 Address 6: Lower Burst Limit (LBL)
  • 7.11 Addresses 7–8: AKS Mask
  • 7.12 Addresses 9–15: Detect0 – Detect6 PWM
  • 7.13 Address 16: LED Detect Hold Time
  • 7.14 Address 17: LED Fade/Key to LED
  • 7.15 Address 18: LED Latch
  • 7.16 Addresses 19–29: Negative Threshold (NTHR)/Negative Hysteresis (NHYST)
  • 7.17 Address 30: Extend Pulse Time
  • 7.18 Addresses 31–41: Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD)
• 8. Specifications
  • 8.1 Absolute Maximum Specifications
  • 8.2 Recommended Operating Conditions
  • 8.3 DC Specifications
  • 8.4 Timing Specifications
  • 8.5 SPI Bus Specifications
    • 8.5.1 General Specifications
    • 8.5.2 Full SPI Mode
    • 8.5.3 Quick SPI Mode
  • 8.6 External Reset
  • 8.7 Internal Resonator
  • 8.8 Power Consumption
  • 8.9 Mechanical Dimensions
    • 8.9.1 AT42QT1110-MZ – 32-pin 5 x 5 mm QFN
    • 8.9.2 AT42QT1110-AZ – 32-pin 7 x 7 mm TQFP
  • 8.10 Marking
    • 8.10.1 AT42QT1110-MZ – 32-pin 5 x 5 mm QFN
    • 8.10.2 AT42QT1110-AZ – 32-pin 7 x 7 mm TQFP
  • 8.11 Part Number
  • 8.12 Moisture Sensitivity Level (MSL)
• Revision History