Document Outline

• Features
• Pin Configuration
  • Disclaimer
• Description
  • Block Diagram
  • Pin Descriptions
    • VCC
    • GND
    • AVCC
    • Port A (PA7..PA0)
    • Port B (PB7..PB0)
    • XTAL1
    • XTAL2
• Architectural Overview
  • General Purpose Register File
    • X-register, Y-register, and Z- register
  • ALU – Arithmetic Logic Unit
  • In-System Programmable Flash Program Memory
  • SRAM Data Memory
  • Program and Data Addressing Modes
    • Register Direct, Single Register Rd
    • Register Direct, Two Registers Rd and Rr
    • I/O Direct
    • Data Direct
    • Data Indirect with Displacement
    • Data Indirect
    • Data Indirect with Pre- decrement
    • Data Indirect with Post- increment
    • Constant Addressing Using the LPM Instruction
    • Indirect Program Addressing, IJMP and ICALL
    • Relative Program Addressing, RJMP and RCALL
  • EEPROM Data Memory
• Memory Access Times and Instruction Execution Timing
• I/O Memory
  • Status Register – SREG
  • Stack Pointer – SP
  • Reset and Interrupt Handling
    • Reset Sources
    • Power-on Reset
    • External Reset
    • Brown-out Detection
    • Watchdog Reset
• System Clock and Clock Options
  • Clock Systems and their Distribution
    • CPU Clock – clkCPU
    • I/O Clock – clkI/O
    • Flash Clock – clkFLASH
    • ADC Clock – clkADC
    • Internal PLL for Fast Peripheral Clock Generation – clkPCK
  • Clock Sources
  • Crystal Oscillator
  • Low-frequency Crystal Oscillator
  • External RC Oscillator
  • Calibrated Internal RC Oscillator
    • Oscillator Calibration Register – OSCCAL
  • External Clock
    • High Frequency PLL Clock – PLLCLK
    • MCU Status Register – MCUSR
    • Interrupt Handling
    • Interrupt Response Time
    • General Interrupt Mask Register – GIMSK
    • General Interrupt Flag Register – GIFR
    • Timer/Counter Interrupt Mask Register – TIMSK
    • Timer/Counter Interrupt Flag Register – TIFR
    • External Interrupt
    • Pin Change Interrupt
    • MCU Control Register – MCUCR
• Power Management and Sleep Modes
  • Idle Mode
  • ADC Noise Reduction Mode
  • Power-down Mode
  • Standby Mode
  • Minimizing Power Consumption
    • Analog to Digital Converter
    • Analog Comparator
    • Brown-out Detector
    • Internal Voltage Reference
    • Watchdog Timer
    • Port Pins
• Timer/Counters
  • Timer/Counter0 Prescaler
  • Timer/Counter1 Prescaler
  • 8-bit Timer/Counter0
    • Timer/Counter0 Control Register – TCCR0
    • Timer/Counter0 – TCNT0
  • 8-bit Timer/Counter1
    • Timer/Counter1 Control Register A – TCCR1A
    • Timer/Counter1 Control Register B – TCCR1B
    • Timer/Counter1 – TCNT1
    • Timer/Counter1 Output Compare RegisterA – OCR1A
    • Timer/Counter1 Output Compare RegisterB – OCR1B
    • Timer/Counter1 Output Compare RegisterC – OCR1C
    • PLL Control and Status Register – PLLCSR
    • Timer/Counter1 Initialization for Asynchronous Mode
    • Timer/Counter1 in PWM Mode
• Watchdog Timer
  • Watchdog Timer Control Register – WDTCR
• EEPROM Read/Write Access
  • EEPROM Address Register – EEAR
  • EEPROM Data Register – EEDR
  • EEPROM Control Register – EECR
  • Preventing EEPROM Corruption
• Universal Serial Interface – USI
  • Overview
  • Register Descriptions
    • USI Data Register – USIDR
    • USI Status Register – USISR
    • USI Control Register – USICR
  • Functional Descriptions
    • Three-wire Mode
    • SPI Master Operation Example
    • SPI Slave Operation Example
    • Two-wire Mode
    • Start Condition Detector
  • Alternative USI Usage
    • Half-duplex Asynchronous Data Transfer
    • 4-bit Counter
    • 12-bit Timer/Counter
    • Edge Triggered External Interrupt
    • Software Interrupt
• Analog Comparator
  • Analog Comparator Control and Status Register – ACSR
• Analog to Digital Converter
  • Features
  • Operation
  • Prescaling and Conversion Timing
  • ADC Noise Canceler Function
  • ADC Conversion Result
    • ADC Multiplexer Selection Register – ADMUX
    • ADC Control and Status Register – ADCSR
    • ADC Data Register – ADCL and ADCH
      • ADLAR = 0
      • ADLAR = 1
  • Scanning Multiple Channels
  • ADC Noise Canceling Techniques
  • Offset Compensation Schemes
• I/O Ports
  • Introduction
  • Ports as General Digital I/O
    • Configuring the Pin
    • Reading the Pin Value
    • Digital Input Enable and Sleep Modes
  • Alternate Port Functions
    • MCU Control Register – MCUCR
    • Alternate Functions of Port A
    • Alternate Functions Of Port B
  • Register Description for I/O Ports
    • Port A Data Register – PORTA
    • Port A Data Direction Register – DDRA
    • Port A Input Pins Address – PINA
    • Port B Data Register – PORTB
    • Port B Data Direction Register – DDRB
    • Port B Input Pins Address – PINB
• Memory Programming
  • Program and Data Memory Lock Bits
  • Fuse Bits
    • Latching of Fuses
  • Signature Bytes
  • Calibration Byte
  • Parallel Programming Parameters, Pin Mapping, and Commands
    • Signal Names
  • Parallel Programming
    • Enter Programming Mode
    • Considerations for Efficient Programming
    • Chip Erase
    • Programming the Flash
    • Programming the EEPROM
    • Reading the Flash
    • Reading the EEPROM
    • Programming the Fuse Low Bits
    • Programming the Fuse High Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
    • Reading the Calibration Byte
    • Parallel Programming Characteristics
  • Serial Downloading
  • Serial Programming Pin Mapping
    • Serial Programming Algorithm
    • Data Polling Flash
    • Data Polling EEPROM
    • Serial Programming Characteristics
• Electrical Characteristics
  • Absolute Maximum Ratings*
  • External Clock Drive Waveforms
  • External Clock Drive
• ADC Characteristics – Preliminary Data
• ATtiny26 Typical Characteristics – Preliminary Data
• ATtiny26/L Register Summary
• Instruction Set Summary 
• Ordering Information(1)
• Packaging Information
  • 20P3
  • 20S
  • 32M1-A
• Data Sheet Change Log for ATtiny26
  • Changes from Rev. 1477A-03/02 to Rev. 1477B-04/02
• Table of Contents