Document Outline

• General Description
• Applications
• Features
• Simplified Operating Circuit
• Absolute Maximum Ratings
• Electrical Characteristics
• Electrical Characteristics: 2-Wire Interface
• I2C Bus Timing Diagram
• Typical Operating Characteristics
• Typical Operating Characteristics
• Pin Configuration
• Pin Description
• Block Diagram
• Detailed Description
• ModelGauge m3 Algorithm
  • OCV Estimation and Coulomb-Count Mixing
  • Fuel-Gauge Empty Compensation
  • Fuel-Gauge Learning
  • Determining Fuel-Gauge Accuracy
  • Initial Accuracy
• Typical Operating Circuit
• Recommended Layout
• ModelGauge m3 Registers
• ModelGauge Algorithm Output Registers
  • SOCMIX Register (0Dh)
  • RemCapMIX Register (0Fh)
  • SOCREP Register (06h)
  • RemCapREP Register (05h)
  • SOCAV Register (0Eh)
  • RemCapAV Register (1Fh)
  • SOCVF Register (FFh)
  • TTE Register (11h)
  • Age Register (07h)
  • Cycles Register (17h)
  • VFOCV Register (FBh)
  • FullCAP Register (10h)
  • FullCapNom Register (23h)
  • QH Register (4Dh)
• Application-Specific Registers
  • DesignCap Register (18h)
  • FullSOCThr Register (13h)
• End-of-Charge Detection
  • ICHGTerm Register (1Eh)
  • V_empty Register (3Ah)
• Cell Characterization Information Registers
• Algorithm Configuration Registers
  • FilterCFG Register (29h)
  • RelaxCFG Register (2Ah)
  • LearnCFG Register (28h)
  • MiscCFG Register (2Bh)
  • FSTAT Register (3Dh)
  • AtRate Register (04h)
• Power-Up and Power-On Reset
  • Save and Restore Registers
• Battery Removal and Insertion
  • Cell Insertion (IC Already Powered)
  • Cell Removal
  • Fast Detection of Cell Removal
• Modes of Operation
• ALRT Function
  • VALRT Threshold Register (01h)
  • TALRT Threshold Register (02h)
  • SALRT Threshold Register (03h)
• Status and Configuration
  • CONFIG Register (1Dh)
  • TIMER Register (3Eh)
  • SHDNTIMER Register (3Fh)
  • Status Register (00h)
  • Version Register (21h)
• Voltage Measurement
  • VCELL Register (09h)
  • AverageVCELL Register (19h)
  • MaxMinVCELL Register (1Bh)
• Current Measurement
  • Current Register (0Ah)
  • AverageCurrent Register (0Bh)
  • MaxMinCurrent Register (1Ch)
  • CGAIN Register 2Eh/COFF Register (2Fh)
• Temperature Measurement
  • AIN Register (27h)
  • Temperature Register (08h)
  • AverageTemperature Register (16h)
  • MaxMinTemperature Register (1Ah)
  • TGAIN Register 2Ch/TOFF Register (2Dh)
• IC Memory Map
• 2-Wire Bus System
  • Bit Transfer
  • Bus Idle
  • START and STOP Conditions
  • Acknowledge Bits
  • Data Order
  • Slave Address
  • Read/Write Bit
  • Bus Timing
  • 2-Wire Command Protocols
  • Basic Transaction Formats
  • Write Data Protocol
  • Read Data Protocol
• Ordering Information
• Package Information
• Revision History
• LIST OF FIGURES
  • Figure 1. IC Bus Timing Diagram
  • Figure 2. ModelGauge m3 Overview
  • Figure 3. ModelGauge m3 OCV and Coulomb-
  • Figure 4. ModelGauge m3 Algorithm Mixing
  • Figure 5. Typical Operating Circuit
  • Figure 6. Operating Circuits that Share
  • Figure 7. Proper Board Layout
  • Figure 8. ModelGauge m3 Register Map
  • Figure 9. SOC Register Format (Output)
  • Figure 10. RemCap Register Format (Outpu
  • Figure 11. SOC Register Format (Output)
  • Figure 12. RemCap Register Format (Outpu
  • Figure 13. SOC Register Format (Output)
  • Figure 14. RemCap Register Format (Outpu
  • Figure 15. SOC Register Format (Output)
  • Figure 16. TTE Register Format (Output)
  • Figure 17. Age Register Format (Output)
  • Figure 18. Cycles Register Format (Outpu
  • Figure 19. VFOCV Register Format (Output
  • Figure 20. FullCAP Register Format (Outp
  • Figure 21. FullCapNom Register Format (O
  • Figure 22. QH Register Format (Output)
  • Figure 23. DesignCap Register Format (In
  • Figure 24. FullSOCThr Register Format (I
  • Figure 25. False End-of-Charge Events
  • Figure 26. FullCAP Learning at End of Ch
  • Figure 27. ICHGTerm Register Format (Inp
  • Figure 28. V_empty Register Format (Inpu
  • Figure 29. FilterCFG Register Format (In
  • Figure 30. RelaxCFG Register Format (Inp
  • Figure 31. Cell Relaxation Detection
  • Figure 32. LearnCFG Register Format (Inp
  • Figure 33. MiscCFG Register Format (Inpu
  • Figure 34. FSTAT Register Format (Output
  • Figure 35. AtRate Register Format (Input
  • Figure 37. Operation After Cell Insertio
  • Figure 38. Fast Detection of Cell Remova
  • Figure 39. MAX17047 State Based on Shutd
  • Figure 40. V Threshold Register Format (
  • Figure 41. T Threshold Register Format (
  • Figure 42. S Threshold Register Format (
  • Figure 43. CONFIG Register Format (Input
  • Figure 44. Timer Register Format (Output
  • Figure 45. SHDNTIMER Register Format (In
  • Figure 46. Status Register Format (Input
  • Figure 47. Version Register Format (Outp
  • Figure 48. V Register Format (Output)
  • Figure 49. AverageV Register Format (Out
  • Figure 50. MaxMinV Register Format (Outp
  • Figure 51. Current Register Format (Outp
  • Figure 52. AverageCurrent Register Forma
  • Figure 53. MaxMinCurrent Register Format
  • Figure 54. CGAIN Register Format (Input)
  • Figure 55. COFF Register Format (Input)
  • Figure 56. AIN Register Format (Output)
  • Figure 57. Temperature Register Format (
  • Figure 58. AverageTemperature Register F
  • Figure 59. MaxMinTemperature Register Fo
  • Figure 60. TGAIN Register Format (Input)
  • Figure 61. TOFF Register Format (Input)
• LIST OF TABLES
  • Table 1. Cell Characterization Informati
  • Table 2. Save and Restore Registers
  • Table 3. Sample Current Register Convers
  • Table 4. Recommended TGAIN and TOFF Regi
  • Table 5. Device Memory Map
  • Table 6. 2-Wire Protocol Key