Document Outline

• Chapter 1 Overview
• Chapter 2 Acronyms
• Chapter 3 Pin Configuration
  • Figure 3.1 USB4640/USB4640i 48-Pin QFN
• Chapter 4 Block Diagram
  • Figure 4.1 USB4640/USB4640i Block Diagram
• Chapter 5 Pin Table
  • 5.1 48-Pin Table
    • Table 5.1 USB4640/USB4640i 48-Pin Table
• Chapter 6 Pin Descriptions
  • 6.1 USB4640/USB4640i Pin Descriptions
    • Table 6.1 USB4640/USB4640i Pin Descriptions
  • 6.2 Buffer Type Descriptions
    • Table 6.2 USB4640/USB4640i Buffer Type Descriptions
  • 6.3 Port Power Control
    • Figure 6.1 Port Power Control with USB Power Switch
    • Figure 6.2 Port Power Control with a Single Poly Fuse and Multiple Loads
    • Figure 6.3 Port Power with Ganged Control with Poly Fuse
  • 6.4 ROM BOOT Sequence
    • Figure 6.4 SPI ROM Connection
    • Figure 6.5 I2C Connection
• Chapter 7 Pin Reset States
  • Figure 7.1 Pin Reset States
  • Table 7.1 Legend for Pin Reset States Table
  • 7.1 Pin Reset States
    • Table 7.2 USB4640/USB4640i Reset States Table
• Chapter 8 Configuration Options
  • 8.1 Hub
    • 8.1.1 Hub Configuration Options
  • 8.2 Card Reader
  • 8.3 System Configurations
    • 8.3.1 EEPROM/SPI Interface
    • 8.3.2 EEPROM Data Descriptor
      • Table 8.1 Internal Flash Media Controller Configurations
      • Table 8.2 Hub Controller Configurations
      • Table 8.3 Other Internal Configurations
  • 8.4 Set bit 7 of bmAttribute to enable the registers in Table 8.4.
    • Table 8.4 Internal Flash Media Controller Extended Configurations
    • 8.4.1 EEPROM Data Descriptor Register Descriptions
    • 8.4.2 A0h-A7h: Device Power Configuration
    • 8.4.3 Device ID Strings
    • 8.4.4 Hub Controller Configurations
      • Table 8.5 Port Map Register for Ports 1 & 2
      • Table 8.6 Port Map Register for Port 3
    • 8.4.5 Internal Flash Media Controller Extended Configurations
    • 8.4.6 I2C EEPROM
    • 8.4.7 In-Circuit EEPROM Programming
  • 8.5 Default Configuration Option
  • 8.6 Reset
    • 8.6.1 Internal POR Hardware Reset
    • 8.6.2 External Hardware nRESET
      • Figure 8.1 nRESET Timing for EEPROM Mode
      • Table 8.7 nRESET Timing for EEPROM Mode
    • 8.6.3 USB Bus Reset
• Chapter 9 AC Specifications
  • 9.1 Oscillator/Crystal
    • Figure 9.1 Typical Crystal Circuit
    • Table 9.1 Crystal Circuit Legend
    • Figure 9.2 Capacitance Formulas
  • 9.2 Ceramic Resonator
    • Figure 9.3 Ceramic Resonator Usage with SMSC IC
  • 9.3 External Clock
    • 9.3.1 I2C EEPROM
    • 9.3.2 USB 2.0
• Chapter 10 DC Parameters
  • 10.1 Maximum Guaranteed Ratings
    • Figure 10.1 Supply Rise Time Model
  • 10.2 Operating Conditions
  • 10.3 DC Electrical Characteristics
  • 10.4 Capacitance
    • Table 10.1 Pin Capacitance
• Chapter 11 GPIO Usage
  • Table 11.1 USB4640/USB4640i GPIO Usage
• Chapter 12 Package Specifications
  • Figure 12.1 USB4640/USB4640i 48-Pin QFN
  • 12.1 Tape and Reel Specifications
    • Figure 12.2 48-Pin Package Tape Specifications
    • Figure 12.3 48-Pin Package Reel Specifications