Document Outline

• Table of Contents
• Preface
• 1 System Control
  • 1.1 Introduction
    • 1.1.1 Block Diagram
    • 1.1.2 CPU Core
    • 1.1.3 FFT Hardware Accelerator
      • 1.1.3.1 Using FFT Accelerator ROM routines
    • 1.1.4 Power Management
    • 1.1.5 Peripherals
  • 1.2 System Memory
    • 1.2.1 Program/Data Memory Map
      • 1.2.1.1 On-Chip Dual-Access RAM (DARAM)
      • 1.2.1.2 On-Chip Single-Access RAM (SARAM)
      • 1.2.1.3 On-Chip Single-Access Read-Only Memory (SAROM)
      • 1.2.1.4 External Memory
        • 1.2.1.4.1 Asynchronous EMIF Interface
      • 1.2.1.5 Synchronous EMIF Interface
    • 1.2.2 I/O Memory Map
  • 1.3 Device Clocking
    • 1.3.1 Overview
    • 1.3.2 Clock Domains
  • 1.4 System Clock Generator
    • 1.4.1 Overview
    • 1.4.2 Functional Description
      • 1.4.2.1 Multiplier and Dividers
      • 1.4.2.2 Powering Down and Powering Up the System PLL
      • 1.4.2.3 CLKOUT Pin
      • 1.4.2.4 DSP Reset Conditions of the System Clock Generator
        • 1.4.2.4.1 Clock Generator During Reset
        • 1.4.2.4.2 Clock Generator After Reset
    • 1.4.3 Configuration
      • 1.4.3.1 BYPASS MODE
        • 1.4.3.1.1 Entering and Exiting the BYPASS MODE
        • 1.4.3.1.2 Register Bits Used in the BYPASS MODE
        • 1.4.3.1.3 Setting the System Clock Frequency In the BYPASS MODE
      • 1.4.3.2 PLL MODE
        • 1.4.3.2.1 Entering and Exiting the PLL MODE
        • 1.4.3.2.2 Register Bits Used in the PLL Mode
        • 1.4.3.2.3 Frequency Ranges for Internal Clocks
        • 1.4.3.2.4 Setting the Output Frequency for the PLL MODE
        • 1.4.3.2.5 Lock Time
        • 1.4.3.2.6 Software Steps To Modify Multiplier and Divider Ratios
    • 1.4.4 Clock Generator Registers
      • 1.4.4.1 Clock Generator Control Register 1 (CGCR1) [1C20h]
      • 1.4.4.2 Clock Generator Control Register 2 (CGCR2) [1C21h]
      • 1.4.4.3 Clock Generator Control Register 3 (CGCR3) [1C22h]
      • 1.4.4.4 Clock Generator Control Register 4 (CGCR4) [1C23h]
      • 1.4.4.5 Clock Configuration Register 1 (CCR1) [1C1Eh]
      • 1.4.4.6 Clock Configuration Register 2 (CCR2) [1C1Fh]
  • 1.5 Power Management
    • 1.5.1 Overview
    • 1.5.2 Power Domains
    • 1.5.3 Clock Management
      • 1.5.3.1 CPU Domain Clock Gating
        • 1.5.3.1.1 Idle Configuration Register (ICR) [0001h] and IDLE Status Register (ISTR) [0002h]
        • 1.5.3.1.2 Valid Idle Configurations
        • 1.5.3.1.3 Clock Configuration Process
      • 1.5.3.2 Peripheral Domain Clock Gating
        • 1.5.3.2.1 Peripheral Clock Gating Configuration Registers (PCGCR1 and PCGCR2) [1C02 - 1C03h]
        • 1.5.3.2.2 Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) [1C3Ah]
        • 1.5.3.2.3 Clock Configuration Process
      • 1.5.3.3 Clock Generator Domain Clock Gating
      • 1.5.3.4 USB Domain Clock Gating
        • 1.5.3.4.1 Clock Configuration Process
        • 1.5.3.4.2 USB System Control Register (USBSCR) [1C32h]
      • 1.5.3.5 RTC Domain Clock Gating
    • 1.5.4 Static Power Management
      • 1.5.4.1 RTC Power Management Register (RTCPMGT) [1930h]
      • 1.5.4.2 RTC Interrupt Flag Register (RTCINTFL) [1920h]
      • 1.5.4.3 Internal Memory Low Power Modes
        • 1.5.4.3.1 RAM Sleep Mode Control Register 1 (RAMSLPMDCNTLR1) [1C28h]
    • 1.5.5 Power Configurations
      • 1.5.5.1 IDLE2 Procedure
      • 1.5.5.2 IDLE3 Procedure
      • 1.5.5.3 Core Voltage Scaling
  • 1.6 Interrupts
    • 1.6.1 IFR and IER Registers
    • 1.6.2 Interrupt Timing
    • 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h]
    • 1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers
    • 1.6.5 DMA Interrupt Enable and Aggregation Flag Registers
  • 1.7 System Configuration and Control
    • 1.7.1 Overview
    • 1.7.2 Device Identification
      • 1.7.2.1 Die ID Register 0 (DIEIDR0) [1C40h]
      • 1.7.2.2 Die ID Register 1 (DIEIDR1) [1C41h]
      • 1.7.2.3 Die ID Register 2 (DIEIDR2) [1C42h]
      • 1.7.2.4 Die ID Register 3 (DIEIDR3[15:0]) [1C43h]
      • 1.7.2.5 Die ID Register 4 (DIEIDR4) [1C44h]
      • 1.7.2.6 Die ID Register 5 (DIEIDR5) [1C45h]
      • 1.7.2.7 Die ID Register 6 (DIEIDR6) [1C46h]
      • 1.7.2.8 Die ID Register 7 (DIEIDR7) [1C47h]
    • 1.7.3 Device Configuration
      • 1.7.3.1 External Bus Selection Register (EBSR)
      • 1.7.3.2 LDO Control Register [7004h]
      • 1.7.3.3 LDO Control
      • 1.7.3.4 Output Slew Rate Control Register (OSRCR) [1C16h]
      • 1.7.3.5 Pull-Up/Pull-Down Inhibit Register (PDINHIBR1, PDINHIBR2, and PDINHIBR3 [1C17h, 1C18h, and 1C19h]
    • 1.7.4 DMA Controller Configuration
      • 1.7.4.1 DMA Synchronization Events
      • 1.7.4.2 DMA Configuration Registers
        • 1.7.4.2.1 DMA Interrupt Flag Register (DMAIFR) [1C30h] and DMA Interrupt Enable Register (DMAIER) [1C31h]
        • 1.7.4.2.2 DMAn Channel Event Source Registers (DMAnCESR1 and DMAnCESR2) [1C1Ah, 1C1Bh, 1C1Ch, 1C1Dh, 1C36h, 1C37h, 1C38h, and 1C39h]
    • 1.7.5 Peripheral Reset
      • 1.7.5.1 Peripheral Software Reset Counter Register (PSRCR) [1C04h]
      • 1.7.5.2 Peripheral Reset Control Register (PRCR) [1C05h]
    • 1.7.6 EMIF and USB Byte Access
      • 1.7.6.1 EMIF System Control Register (ESCR) [1C33h]
    • 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h]