Document Outline

• ISCC User Manual
  • Revision History
  • Table of Contents
  • Chapter 1 General Description
    • 1.1 INTRODUCTION
    • 1.2 Features
    • 1.3 Pin Description
  • Chapter 2 Interfacing the ISCC™
    • 2.1 Introduction
    • 2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION
      • 2.2.1 Non-Multiplexed Bus Operation
      • 2.2.2 Multiplexed Bus Operation
      • 2.2.3 Data Transfers
    • 2.3 I/O INTERFACE CAPABILITIES
      • 2.3.1 Polling
      • 2.3.2 Interrupts
      • 2.3.3 DMA Interrupts
    • 2.4 REGISTER ACCESS
      • 2.4.1 SCC Cell Register Access, Multiplexed Bus
      • 2.4.2 SCC Cell Register Access, Non-Multiplexed Bus
      • 2.4.3 SCC Cell Register Reset
      • 2.4.4 DMA Cell Registers
      • 2.4.5 DMA Register Access, Multiplexed Bus
      • 2.4.6 DMA Register Access, Non-Multiplexed Bus Mode
      • 2.4.7 Notes on Pointer Accesses
  • Chapter 3 ISCC™ DMA and Ancillary Support Circuitry
    • 3.1 INTRODUCTION
    • 3.2 DMA
      • 3.2.1 Receiver DMA Operation
      • 3.2.2 Transmitter DMA Operation
    • 3.3 BAUD RATE GENERATOR
    • 3.4 DATA ENCODING/DECODING
    • 3.5 DIGITAL PHASE-LOCKED LOOP (DPLL)
      • 3.5.1 DPLL Operation in the NRZI Mode
      • 3.5.2 DPLL Operation in the FM Modes
      • 3.5.3 DPLL Operation and Encoding in the Manchester Mode
    • 3.6 CLOCK SELECTION
    • 3.7 CRYSTAL OSCILLATORS
  • Chapter 4 Data Communication Modes
    • 4.1 INTRODUCTION
      • 4.1.1 General Description of the Transmitter
      • 4.1.2 General Description of the Receiver
    • 4.2 ASYNCHRONOUS MODE
      • 4.2.1 Asynchronous Transmit
      • 4.2.2 Asynchronous Reception
    • 4.3 BYTE-ORIENTED SYNCHRONOUS MODE
      • 4.3.1 Byte Oriented Synchronous Transmit
      • 4.3.2 Byte-Oriented Synchronous Receive
      • 4.3.3 Transmitter/Receiver Synchronization
    • 4.4 BIT-ORIENTED SYNCHRONOUS MODE
      • 4.4.1 SDLC Transmit
      • 4.4.2 SDLC Receive
      • 4.4.3 SDLC LOOP MODE
      • 4.4.4 SDLC Loop Mode Receive
      • 4.4.5 SDLC Loop Mode Transmit
  • Chapter 5 Register Descriptions
    • 5.1 INTRODUCTION
    • 5.2 REGISTER DESCRIPTIONS
      • 5.2.1 Write Registers, SCC Cell
      • 5.2.2 Read Registers, SCC Cell
      • 5.2.3 DMA Registers
    • 5.3 SCC CELL REGISTER OVERVIEW
    • 5.4 WRITE REGISTERS
      • 5.4.1 Write Register 0 (Command Register)
      • 5.4.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition)
      • 5.4.3 Write Register 2 (Interrupt Vector)
      • 5.4.4 Write Register 3 (Receive Parameters and Control)
      • 5.4.5 Write Register 4 (Transmit/Receiver Miscellaneous Parameters and Modes)
      • 5.4.6 Write Register 5 (Transmit Parameter and Controls)
      • 5.4.7 Write Register 6 (Sync Characters or SDLC Address Field)
      • 5.4.8 Write Register 7 (SYNC Character or SDLC Flag)
      • 5.4.9 Write Register 8 (Transmit Buffer)
      • 5.4.10 Write Register 9 (Master Interrupt Control)
      • 5.4.11 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits)
      • 5.4.12 Write Register 11 (Clock Mode Control)
      • 5.4.13 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant)
      • 5.4.14 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant)
      • 5.4.15 Write Register 14 (Miscellaneous Control Bits)
      • 5.4.16 Write Register 15 (External/Status Interrupt Control)
    • 5.5 READ REGISTERS
      • 5.5.1 Read Register 0 (Transmit/receive buffer Status and External Status)
      • 5.5.2 Read Register 1
      • 5.5.3 Read Register 2
      • 5.5.4 Read Register 3
      • 5.5.5 Read Register 8
      • 5.5.6 Read Register 10
      • 5.5.7 Read Register 12
      • 5.5.8 Read Register 13
      • 5.5.9 Read Register 15
    • 5.6 DMA CELL REGISTER DESCRIPTIONS
      • 5.6.1 Channel Command/Address Register
      • 5.6.2 DMA Status Register
      • 5.6.3 Interrupt Control Register
      • 5.6.4 Interrupt Vector Register
      • 5.6.5 Interrupt Command Register
      • 5.6.6 Interrupt Status Register
      • 5.6.7 DMA Enable Register
      • 5.6.8 DMA Control Register
      • 5.6.9 Receive DMA Count Registers A, B
      • 5.6.10 Transmit DMA Count Registers A, B
      • 5.6.11 Receive DMA Address Registers A, B
      • 5.6.12 Transmit DMA Address Registers A, B
      • 5.6.13 Bus Configuration Register
    • Customer Support
• App Note - Interfacing Z80 CPUs to Z8500
• App Note - Z180 Interfaced with SCC at MHZ
• App Note - Zilog Datacom Family with 80186 CPU
• App Note - SCC in Binary Syn Communications
• App Note - Serial Communications Controller SDLC Mode of Operation
• App Note - Using SCC with Z8000 in SDLC Protocol
• App Note - Boost Your System Performance Using Zilog ESCC
• App Note - Technical Considerations When Implementing LocalTalk Link Access Protocol
• App Note - On-Chip Oscillator Design
• App Note - Interfacing the ISCC to the 68000 and 8086
• ISCC Controller - Questions and Answers