Document Outline

• SCC/ESCC User Manual
  • Table of Contents
    • General Description
      • Introduction
      • SCC’s Capabilities
      • Block Diagram
      • Pin Descriptions
        • Pin Descriptions
        • Pins Common to both Z85X30 and Z80X30
        • Pin Descriptions, (Z85X30 Only)
        • Pin Descriptions, (Z80X30 Only)
    • Interfacing the SCC/ESCC
      • Introduction
      • Z80X30 Interface Timing
        • Z80X30 Read Cycle Timing
        • Z80X30 Write Cycle Timing
        • Z80X30 Interrupt Acknowledge Cycle Timing
        • Z80X30 Register Access
        • Z80C30 Register Enhancement
        • Z80230 Register Enhancements
        • Z80X30 Reset
      • Z85X30 Interface Timing
        • Z85X30 Read Cycle Timing
        • Z85X30 Write Cycle Timing
        • Z85X30 Interrupt Acknowledge Cycle Timing
        • Z85X30 Register Access
        • Z85C30 Register Enhancement
        • Z85C30/Z85230/L Register Enhancements
        • Z85X30 Reset
      • Interface Programming
        • I/O Programming Introduction
        • Polling
        • Interrupts
        • Interrupt Control
        • Daisy-Chain Resolution
        • Interrupt Acknowledge
        • The Receiver Interrupt
        • Transmit Interrupts and Transmit Buffer Empty Bit
        • External/Status Interrupts
      • Block/DMA Transfer
        • Block Transfers
        • DMA Requests
      • Test Functions
        • Local Loopback
        • Auto Echo
    • SCC/ESCC Ancillary Support Circuitry
      • Introduction
      • Baud Rate Generator
      • Data Encoding/Decoding
      • DPLL Digital Phase-Locked Loop
        • DPLL Operation in the NRZI Mode
        • DPLL Operation in the FM Modes
        • DPLL Operation in the Manchester Mode
        • Transmit Clock Counter (ESCC only)
      • Clock Selection
      • Crystal Oscillator
    • Data Communication Modes
      • Introduction
        • Transmit Data Path Description
        • Receive Data Path Description
      • Asynchronous Mode
        • Asynchronous Transmit
        • Asynchronous Receive
        • Asynchronous Initialization
      • Byte-Oriented Synchronous Mode
        • Byte-Oriented Synchronous Transmit
        • Byte-Oriented Synchronous Receive
        • Transmitter/Receiver Synchronization
      • Bit-oriented Synchronous (SDLC/HDLC) Mode
        • SDLC Transmit
        • SDLC Receive
        • SDLC Frame Status FIFO
        • SDLC Loop Mode
    • Register Descriptions
      • Introduction
      • Write Registers
        • Write Register 0 (Command Register)
        • Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition)
        • Write Register 2 (Interrupt Vector)
        • Write Register 3 (Receive Parameters and Control)
        • Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes)
        • Write Register 5 (Transmit Parameters and Controls)
        • Write Register 6 (Sync Characters or SDLC Address Field)
        • Write Register 7 (Sync Character or SDLC Flag)
        • Write Register 7 Prime (ESCC only)
        • Write Register 7 Prime (85C30 Only)
        • Write Register 8 (Transmit Buffer)
        • Write Register 9 (Master Interrupt Control)
        • Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits)
        • Write Register 11 (Clock Mode Control)
        • Write Register 12 (Lower Byte of Baud Rate Generator Time Constant)
        • Write Register 13 (Upper Byte of Baud Rate Generator Time Constant)
        • Write Register 14 (Miscellaneous Control Bits)
        • Write Register 15 (External/Status Interrupt Control)
      • Read Registers
        • Read Register 0 (Transmit/Receive Buffer Status and External Status)
        • Read Register 1
        • Read Register 2
        • Read Register 3
        • Read Register 4 (ESCC and 85C30 Only)
        • Read Register 5 (ESCC and 85C30 Only)
        • Read Register 6 (Not on NMOS)
        • Read Register 7 (Not on NMOS)
        • Read Register 8
        • Read Register 9 (ESCC and 85C30 Only)
        • Read Register 10
        • Read Register 11 (ESCC and 85C30 Only)
        • Read Register 12
        • Read Register 13
        • Read Register 14 (ESCC and 85C30 Only)
        • Read Register 15
    • Application Notes
      • Interfacing Z80® CPUs to the Z8500 Peripheral Family
      • AN0096: The Z180 Interfaced with the SCC at 10 MHz
      • AN0097: The Zilog® Datacom Family with the 80186 CPU
      • SCC in Binary Synchronous Communications
      • Serial Communication Controller (SCC): SDLC Mode of Operation
      • Using SCC with Z8000 in SDLC Protocol
      • AN0300: Boost Your System Performance Using the Zilog ESCC Controller
      • AN006: Technical Considerations When Implementing Localtalk Link Access Protocol
      • AN0075: On-Chip Oscillator Design
      • Interfacing the ISCC to the 68000 and 8086
      • Zilog SCC Z8030/Z8530 Questions and Answers
      • Zilog ESCC Controller Questions and Answers
    • Questions and Answers
      • Zilog SCC Z8030/Z8530 Questions and Answers
      • Zilog ESCC Controller Questions and Answers
    • Customer Support